公开(公告)号：US06743655B2

公开(公告)日：2004-06-01

申请号：US10205527

申请日：2002-07-25

申请人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

发明人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

IPC分类号： H01L2100

CPC分类号： H01L31/028 ,  H01L31/0352 ,  Y02E10/547

摘要： A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.

摘要翻译： 描述了在偏压和照明时呈现光诱导的负微分电阻区域的光电二极管。 光电二极管包括N +硅衬底，形成在N +硅衬底上的氮化硅层，形成在氮化硅层上的再氧化氮化物层和形成在再氧化氮化物层的至少一部分上的N +多晶硅层。

公开(公告)号：US06445021B1

公开(公告)日：2002-09-03

申请号：US09665913

申请日：2000-09-20

申请人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

发明人： Fen Chen ,  Roger Aime Dufresne ,  Baozhen Li ,  Alvin Wayne Strong

IPC分类号： H01L27148

CPC分类号： H01L31/028 ,  H01L31/0352 ,  Y02E10/547

摘要： A photodiode that exhibits a photo-induced negative differential resistance region upon biasing and illumination is described. The photodiode includes an N+ silicon substrate, a silicon nitride layer formed on the N+ silicon substrate, a reoxidized nitride layer formed on the silicon nitride layer and a N+ polysilicon layer formed on at least a portion of the reoxidized nitride layer.

公开(公告)号：US5898706A

公开(公告)日：1999-04-27

申请号：US846989

申请日：1997-04-30

申请人： Roger Aime Dufresne ,  Charles William Griffin ,  Chorng-Lii Hwang ,  William Alan Klaasen ,  Alvin Wayne Strong

发明人： Roger Aime Dufresne ,  Charles William Griffin ,  Chorng-Lii Hwang ,  William Alan Klaasen ,  Alvin Wayne Strong

IPC分类号： G01R31/28 ,  G01R31/12

CPC分类号： G01R31/2877 ,  G01R31/2856

摘要： The present invention is directed to an apparatus and method for reliability testing of an integrated circuit. The present invention provides a test structure and method for testing gate and node dielectrics of an integrated circuit wherein a self-heating gate structure is integrated with the product structure itself. Selected conductive lines within the product structure are used as heater elements to provide temperature stressing of the integrated circuit. The localized self-heating gate structure is an integral part of the product chip. Thus, etch and deposition characteristics of the test structure are kept identical to the etch and deposition characteristics of the product itself. As low-voltage technologies make it harder to obtain significant acceleration due to voltage stressing, temperature stressing may be used instead to increase acceleration.

摘要翻译： 本发明涉及一种用于集成电路的可靠性测试的装置和方法。 本发明提供了一种用于测试集成电路的栅极和节点电介质的测试结构和方法，其中自加热栅结构与产品结构本身集成。 产品结构内的所选导线用作加热元件，以提供集成电路的温度应力。 局部自加热门结构是产品芯片的组成部分。 因此，测试结构的蚀刻和沉积特性保持与产品本身的蚀刻和沉积特性相同。 由于低压技术使得由于电压应力而难以获得显着的加速度，所以可以使用温度应力来增加加速度。