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    Charged balanced devices with shielded gate trench
    2.
    发明授权
    Charged balanced devices with shielded gate trench 有权
    带屏蔽栅极沟槽的均衡器件

    公开(公告)号：US09356134B2

    公开(公告)日：2016-05-31

    申请号：US14312687

    申请日：2014-06-24

    申请人： François Hébert

    发明人： François Hébert

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

    CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734

    摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

    摘要翻译： 本发明公开了一种设置在半导体衬底上的半导体功率器件，包括具有填充所述深沟槽的外延层的多个深沟槽和覆盖半导体衬底上的所述深沟槽的顶表面之上的区域的同时生长的顶部外延层。 设置在所述顶部外延层中的多个沟槽MOSFET单元，顶部外延层用作主体区域，并且半导体衬底用作漏极区域，由此通过深沟槽中的外延层之间的电荷平衡和 半导体衬底中的与深沟槽横向相邻的区域。 每个沟槽MOSFET单元还包括沟槽栅极和栅极屏蔽掺杂剂区域，其设置在用于每个沟槽MOSFET单元的每个沟槽栅极的下方并基本对齐，用于在电压击穿期间屏蔽沟槽栅极。

    Source and body contact structure for trench-DMOS devices using polysilicon
    3.
    发明授权
    Source and body contact structure for trench-DMOS devices using polysilicon 有权
    使用多晶硅的沟槽DMOS器件的源和体接触结构

    公开(公告)号：US08703563B2

    公开(公告)日：2014-04-22

    申请号：US13559490

    申请日：2012-07-26

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD
    4.
    发明申请
    SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD 有权
    超自对准TRENCH-DMOS结构和方法

    公开(公告)号：US20140004671A1

    公开(公告)日：2014-01-02

    申请号：US13709614

    申请日：2012-12-10

    申请人： François Hébert

    发明人： François Hébert

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66734 ,  H01L21/2257 ,  H01L29/04 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7813

    摘要： A body layer is formed in an epitaxial layer and a gate electrode formed in a trench in the body and epitaxial layer. A gate insulator is disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the epitaxial layer. A cap insulator is disposed on top of the gate electrode. A doped spacer is disposed along a sidewall of the source and a sidewall of the gate insulator. The body layer next to the polysilicon spacer is etched back below the bottom of the polysilicon spacer. Dopants are diffused from the spacer to form the source region.

    摘要翻译： 主体层形成在外延层中，形成在主体和外延层中的沟槽中的栅电极。 栅极绝缘体沿着栅极电极的侧壁设置在栅电极和源极之间，在栅电极和P体之间以及栅电极和外延层之间。 盖绝缘体设置在栅电极的顶部。 掺杂间隔物沿着源极的侧壁和栅极绝缘体的侧壁设置。 多晶硅间隔物旁边的主体层被蚀刻回多晶硅间隔物的底部之下。 掺杂剂从间隔物扩散以形成源区。

    SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON
    6.
    发明申请
    SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON 有权
    使用POLYSILICON的TRENCH-DMOS器件的源和体接触结构

    公开(公告)号：US20120286356A1

    公开(公告)日：2012-11-15

    申请号：US13559490

    申请日：2012-07-26

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

    摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    High power and high temperature semiconductor power devices protected by non-uniform ballasted sources
    9.
    发明授权
    High power and high temperature semiconductor power devices protected by non-uniform ballasted sources 有权
    由不均匀的压载源保护的大功率和高温半导体功率器件

    公开(公告)号：US08110472B2

    公开(公告)日：2012-02-07

    申请号：US13199251

    申请日：2011-08-23

    申请人： François Hébert ,  Anup Bhalla

    发明人： François Hébert ,  Anup Bhalla

    IPC分类号： H01L21/331 ,  H01L21/8222

    CPC分类号： H01L29/7802 ,  H01L24/05 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/7803 ,  H01L2224/0603 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.

    摘要翻译： 半导体功率器件形成在半导体衬底上。 半导体功率器件包括分布在不同区域上的多个晶体管单元，其具有取决于每个不同区域中的局部散热的不同量的镇流电阻。 示例性实施例具有在周边区域附近形成的具有较低的镇流电阻的晶体管电池，并且在接合焊盘区域附近形成具有较高耐压电性的晶体管电池。 另一个示例性实施例包括形成在引线焊盘周围的区域中具有最高镇流电阻的电池，具有较低电阻的晶体管单元形成在连接到用于散热的接合线的引线接合焊盘下方，并且具有最低的晶体管电池 在距离接合焊盘的区域中形成耐压性。

    Inverted-trench grounded-source FET structure with trenched source body short electrode
    10.
    发明授权
    Inverted-trench grounded-source FET structure with trenched source body short electrode 有权
    反沟槽接地源FET结构，具有沟槽源体短路电极

    公开(公告)号：US08008716B2

    公开(公告)日：2011-08-30

    申请号：US11522669

    申请日：2006-09-17

    申请人： Sik K Lui ,  François Hébert ,  Anup Bhalla

    发明人： Sik K Lui ,  François Hébert ,  Anup Bhalla

    IPC分类号： H01L29/66

    CPC分类号： H01L29/781 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

    摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉降通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。