Abstract:
An inductance formed in a stack of insulating layers, the inductance comprising first and second access terminals and first and second half-loops distributed in the stack of insulating layers on a number of distinct levels greater than or equal to four. For each level, each first half-loop is at least partly symmetrical to one of the second half-loops. All the first half-loops are series-connected according to a first succession of first half-loops to form first loops between the first access terminal and a midpoint and all the second half-loops are series-connected according to a second succession of second half-loops to form second loops between the second output terminal and the midpoint.
Abstract:
An inductor formed in a stacking of insulating layers. The inductor comprises first and second access terminals, at least first and second interlaced loops on a first level, and at least third and fourth interlaced loops on a second level distinct from the first level. The third loop is the symmetrical of the first loop with respect to a plane. The fourth loop is the symmetrical of the second loop with respect to said plane. The internal ends of the first and second loops are connected to the internal ends of the third and fourth loops. The external ends of the first and third loops are connected to the first and second access terminals. The external ends of the second and fourth loops are interconnected.
Abstract:
An electronic device includes a semiconductor component having a support substrate in the form of a wafer. On one side of this substrate integrated circuits including an RF circuit and an antenna connected to this RF circuit are formed. A metal layer is situated on the other side of the substrate, facing the antenna. At least on metal via is provided in a through-hole in the substrate, this via being connected at one end to the metal layer and at the other end to the RF circuit, at the same reference potential node as the antenna.
Abstract:
An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.
Abstract:
Integrated inductive device comprising a central loop arranged between two outer loops mutually coupled to the central loop so as to form two patterns roughly in the form of an eight having a common portion corresponding to said central loop.
Abstract:
A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.
Abstract:
An inductance formed in a stacking of insulating layers, the inductance comprising first and second half-turns, each first half-turn being at least partly symmetrical to one of the second half-turns, the first half-turns being distributed in first groups of first half-turns at least partly aligned along the insulating layer stacking direction and the second half-turns being distributed in second groups of second half-turns at least partly aligned along the insulating layer stacking direction. For any pair of first adjacent half-turns of a same group, one of the first half-turns in the pair is electrically series-connected to the other one of the first half-turns in the pair by a single second half turn and for each pair of second adjacent half-turns of a same group, one of the second half-turns in the pair is electrically series-connected to the other one of the second half-turns in the pair by a single first half-turn.
Abstract:
A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.
Abstract:
Integrated inductive device comprising a central loop arranged between two outer loops mutually coupled to the central loop so as to form two patterns roughly in the form of an eight having a common portion corresponding to said central loop.
Abstract:
An inductor formed in a stacking of insulating layers. The inductor comprises first and second access terminals, at least first and second interlaced loops on a first level, and at least third and fourth interlaced loops on a second level distinct from the first level. The third loop is the symmetrical of the first loop with respect to a plane. The fourth loop is the symmetrical of the second loop with respect to said plane. The internal ends of the first and second loops are connected to the internal ends of the third and fourth loops. The external ends of the first and third loops are connected to the first and second access terminals. The external ends of the second and fourth loops are interconnected.