公开(公告)号：US20090027150A1

公开(公告)日：2009-01-29

申请号：US12179847

申请日：2008-07-25

Applicant: Frederic Gianesello

Inventor： Frederic Gianesello

IPC: H01F27/28

CPC classification number: H01F17/0013 ,  H01F21/12 ,  H01F27/34 ,  H01F2021/125 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductance formed in a stack of insulating layers, the inductance comprising first and second access terminals and first and second half-loops distributed in the stack of insulating layers on a number of distinct levels greater than or equal to four. For each level, each first half-loop is at least partly symmetrical to one of the second half-loops. All the first half-loops are series-connected according to a first succession of first half-loops to form first loops between the first access terminal and a midpoint and all the second half-loops are series-connected according to a second succession of second half-loops to form second loops between the second output terminal and the midpoint.

Abstract translation: 电感形成在一叠绝缘层中，该电感包括第一和第二接入端以及分布在绝缘层堆叠中的第一和第二半环，其数量大于或等于四个。 对于每个级别，每个第一半环至少部分地与第二半环中的一个对称。 所有第一半环根据第一连续的第一半环串联连接，以在第一接入终端和中点之间形成第一环路，并且所有第二半环路根据第二连续的第二连续序列连接 半环形成第二输出端和中点之间的第二环。

公开(公告)号：US07986210B2

公开(公告)日：2011-07-26

申请号：US12584510

申请日：2009-09-08

Applicant: Frederic Gianesello

Inventor： Frederic Gianesello

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01F2021/125 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor formed in a stacking of insulating layers. The inductor comprises first and second access terminals, at least first and second interlaced loops on a first level, and at least third and fourth interlaced loops on a second level distinct from the first level. The third loop is the symmetrical of the first loop with respect to a plane. The fourth loop is the symmetrical of the second loop with respect to said plane. The internal ends of the first and second loops are connected to the internal ends of the third and fourth loops. The external ends of the first and third loops are connected to the first and second access terminals. The external ends of the second and fourth loops are interconnected.

Abstract translation: 电感器形成在绝缘层的层叠中。 电感器包括第一和第二接入终端，第一级上至少第一和第二隔行环，以及与第一级不同的第二级上的至少第三和第四隔行环。 第三个回路是第一个回路相对于一个平面的对称。 第四回路是相对于所述平面对称的第二回路。 第一和第二回路的内端连接到第三和第四回路的内端。 第一和第三回路的外部端部连接到第一和第二接入端子。 第二和第四回路的外部端部相互连接。

公开(公告)号：US20110109521A1

公开(公告)日：2011-05-12

申请号：US12941292

申请日：2010-11-08

Applicant: Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

Inventor： Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

IPC: H01Q1/48

CPC classification number: G06K19/07749 ,  G06K19/07771 ,  H01L23/481 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/014

Abstract: An electronic device includes a semiconductor component having a support substrate in the form of a wafer. On one side of this substrate integrated circuits including an RF circuit and an antenna connected to this RF circuit are formed. A metal layer is situated on the other side of the substrate, facing the antenna. At least on metal via is provided in a through-hole in the substrate, this via being connected at one end to the metal layer and at the other end to the RF circuit, at the same reference potential node as the antenna.

Abstract translation: 电子器件包括具有晶片形式的支撑衬底的半导体部件。 在该衬底的一侧形成包括RF电路和连接到该RF电路的天线的集成电路。 金属层位于基板的另一侧，面向天线。 至少在金属通孔中设置在基板的通孔中，该通孔在一端与金属层连接，另一端连接到与RF天线相同的参考电位节点。

公开(公告)号：US20090284331A1

公开(公告)日：2009-11-19

申请号：US12468627

申请日：2009-05-19

Applicant: Sebastien Pruvost ,  Frederic Gianesello

Inventor： Sebastien Pruvost ,  Frederic Gianesello

IPC: H01P3/00 ,  H01P5/00

CPC classification number: H01P3/003 ,  H01P3/006 ,  H01P3/082

Abstract: An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.

Abstract translation: 一个实施例涉及一种共面波导电子器件，其包括其上安装有信号带和至少一个接地平面的衬底。 信号带包括电连接在一起的相同级别的金属化的多条信号线，并且接地平面由导电材料制成并且包括多个孔。

公开(公告)号：US09019065B2

公开(公告)日：2015-04-28

申请号：US12876595

申请日：2010-09-07

Applicant: Frederic Gianesello

Inventor： Frederic Gianesello

IPC: H01F27/28 ,  H01F5/00 ,  H01F17/00 ,  H01F27/34

CPC classification number: H01F17/0006 ,  H01F27/346 ,  H01F2017/0073 ,  H01F2017/0086

Abstract: Integrated inductive device comprising a central loop arranged between two outer loops mutually coupled to the central loop so as to form two patterns roughly in the form of an eight having a common portion corresponding to said central loop.

Abstract translation: 集成感应装置包括布置在两个相互耦合到中心环的外环之间的中央环，以便形成大致具有对应于所述中心环的公共部分的八形形式的两个图案。

公开(公告)号：US08581412B2

公开(公告)日：2013-11-12

申请号：US12896558

申请日：2010-10-01

Applicant: Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

Inventor： Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

IPC: H01L23/48

CPC classification number: H01P3/121 ,  H01P1/207 ,  H01P5/107

Abstract: A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.

Abstract translation: 半导体器件包括衬底。 在该基板的至少一个面上形成集成电路。 还包括至少一个电磁波导，该波导包括两个金属板，这两个金属板被放置在基板厚度的至少一部分的任一侧上并且彼此相对定位。 两个纵向壁彼此相对地放置并且由在其厚度方向上穿过基板的孔中形成的金属通孔形成。 金属通孔电连接两个金属板。

公开(公告)号：US07768372B2

公开(公告)日：2010-08-03

申请号：US12218670

申请日：2008-07-17

Applicant: Frederic Gianesello

Inventor： Frederic Gianesello

IPC: H01F5/00 ,  H01F27/29 ,  H01F27/28

CPC classification number: H01F17/0013 ,  H01F27/34 ,  H01F2021/125 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductance formed in a stacking of insulating layers, the inductance comprising first and second half-turns, each first half-turn being at least partly symmetrical to one of the second half-turns, the first half-turns being distributed in first groups of first half-turns at least partly aligned along the insulating layer stacking direction and the second half-turns being distributed in second groups of second half-turns at least partly aligned along the insulating layer stacking direction. For any pair of first adjacent half-turns of a same group, one of the first half-turns in the pair is electrically series-connected to the other one of the first half-turns in the pair by a single second half turn and for each pair of second adjacent half-turns of a same group, one of the second half-turns in the pair is electrically series-connected to the other one of the second half-turns in the pair by a single first half-turn.

Abstract translation: 电感形成在绝缘层的层叠中，电感包括第一和第二半匝，每个前半匝至少部分地与第二匝之一对称，第一匝分布在第一组中 所述第一半匝至少部分地沿所述绝缘层层叠方向排列，并且所述第二半匝分布在沿所述绝缘层堆叠方向至少部分对准的第二组第二半匝中。 对于相同组的任何一对第一相邻半匝，该对中的第一半匝之一中的一个第一半匝中的一个与该对中的另一个第一半匝电连接单个第二半匝，并且对于 同一组中的每对第二相邻半匝，该对中的第二半匝中的一个通过单个第一半匝电连接到该对中的另一个第二半匝。

公开(公告)号：US20110084398A1

公开(公告)日：2011-04-14

申请号：US12896558

申请日：2010-10-01

Applicant: Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

Inventor： Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

IPC: H01L23/48

CPC classification number: H01P3/121 ,  H01P1/207 ,  H01P5/107

Abstract: A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.

Abstract translation: 半导体器件包括衬底。 在该基板的至少一个面上形成集成电路。 还包括至少一个电磁波导，该波导包括两个金属板，这两个金属板被放置在基板厚度的至少一部分的任一侧上并且彼此相对定位。 两个纵向壁彼此相对地放置并且由在其厚度方向上穿过基板的孔中形成的金属通孔形成。 金属通孔电连接两个金属板。

公开(公告)号：US20110057759A1

公开(公告)日：2011-03-10

申请号：US12876595

申请日：2010-09-07

Applicant: Frederic Gianesello

Inventor： Frederic Gianesello

IPC: H01F27/28

CPC classification number: H01F17/0006 ,  H01F27/346 ,  H01F2017/0073 ,  H01F2017/0086

Abstract: Integrated inductive device comprising a central loop arranged between two outer loops mutually coupled to the central loop so as to form two patterns roughly in the form of an eight having a common portion corresponding to said central loop.

Abstract translation: 集成感应装置包括布置在两个相互耦合到中心环的外环之间的中央环，以便形成大致具有对应于所述中心环的公共部分的八形形式的两个图案。

公开(公告)号：US20100073118A1

公开(公告)日：2010-03-25

申请号：US12584510

申请日：2009-09-08

Applicant: Frederic Gianesello

Inventor： Frederic Gianesello

IPC: H01F27/28

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01F2021/125 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor formed in a stacking of insulating layers. The inductor comprises first and second access terminals, at least first and second interlaced loops on a first level, and at least third and fourth interlaced loops on a second level distinct from the first level. The third loop is the symmetrical of the first loop with respect to a plane. The fourth loop is the symmetrical of the second loop with respect to said plane. The internal ends of the first and second loops are connected to the internal ends of the third and fourth loops. The external ends of the first and third loops are connected to the first and second access terminals. The external ends of the second and fourth loops are interconnected.

Abstract translation: 电感器形成在绝缘层的层叠中。 电感器包括第一和第二接入终端，第一级上至少第一和第二隔行环，以及与第一级不同的第二级上的至少第三和第四隔行环。 第三个回路是第一个回路相对于一个平面的对称。 第四回路是相对于所述平面对称的第二回路。 第一和第二回路的内端连接到第三和第四回路的内端。 第一和第三回路的外部端部连接到第一和第二接入端子。 第二和第四回路的外部端部相互连接。