公开(公告)号：US09728600B2

公开(公告)日：2017-08-08

申请号：US14851355

申请日：2015-09-11

Applicant: Freescale Semiconductor, Inc.

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/22 ,  H01L21/768 ,  H01L29/36 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L29/0634 ,  H01L21/22 ,  H01L21/76 ,  H01L21/761 ,  H01L23/528 ,  H01L27/0251 ,  H01L29/063 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/365 ,  H01L29/402 ,  H01L29/66689 ,  H01L29/7823 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area, and a body region disposed in the semiconductor substrate within the core device area, and in which a channel is formed during operation. The body region is electrically tied to the isolation contact region. The body region and the doped isolation barrier have a common conductivity type. The body region is electrically isolated from the doped isolation barrier within the core device area. The doped isolation barrier and the isolation contact region are not electrically tied to one another such that the doped isolation barrier is biased at a different voltage level than the isolation contact region.

公开(公告)号：US09691880B2

公开(公告)日：2017-06-27

申请号：US15340848

申请日：2016-11-01

Applicant: Freescale Semiconductor, Inc.

Inventor： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-kai Zuo

IPC: H01L31/062 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/66681 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

公开(公告)号：US20170125584A1

公开(公告)日：2017-05-04

申请号：US14926500

申请日：2015-10-29

Applicant: Freescale Semiconductor, Inc.

Inventor： Zhihong Zhang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/76 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/76 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.

公开(公告)号：US09761707B1

公开(公告)日：2017-09-12

申请号：US15242322

申请日：2016-08-19

Applicant: Freescale Semiconductor, Inc.

Inventor： Xin Lin ,  Ronghua Zhu ,  Hongning Yang

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/665 ,  H01L29/7835

Abstract: A device formed in a semiconductor substrate is disclosed. The device include a core device formed in the semiconductor substrate, a first deep trench isolation barrier surrounding the core device and a secondary device formed in the semiconductor substrate outside the deep trench isolation barrier. The device also includes a second deep trench isolation barrier formed to isolate the secondary device from remaining part of the semiconductor substrate. A first portion of the secondary device is electrically connected to a first portion of the core device through a first electrical connector and a second portion of the secondary device is electrically connected to a second portion of the core device through a second electrical connector.

公开(公告)号：US09680011B2

公开(公告)日：2017-06-13

申请号：US14926500

申请日：2015-10-29

Applicant: Freescale Semiconductor, Inc.

Inventor： Zhihong Zhang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC: H01L21/76 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/76 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.

公开(公告)号：US09614041B1

公开(公告)日：2017-04-04

申请号：US14851877

申请日：2015-09-11

Applicant: Freescale Semiconductor Inc.

Inventor： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/66484 ,  H01L29/66492 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

Abstract: A semiconductor device includes a substrate having a first dopant type, a first gate electrode and second gate electrode formed over the substrate and spatially separated from each other, a first region of a second dopant type, having a pocket of the first dopant type, formed in the substrate between the first and second gate electrodes, the pocket being spaced apart from the first and second gate electrodes, a silicide block over the first region, a source region formed in the substrate on an opposing side of the first gate electrode from the first region and having the second dopant type, a drain region formed in the substrate on an opposing side of the second gate electrode from the first region, the drain region having the second dopant type, and a second pocket of the first dopant type formed in the drain region adjacent to the second gate electrode.

公开(公告)号：US09590097B2

公开(公告)日：2017-03-07

申请号：US15053745

申请日：2016-02-25

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66689 ,  H01L29/7835 ,  H01L29/78624

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.

Abstract translation: 提供半导体器件结构和相关的制造方法。 示例性的半导体器件结构包括具有第一导电类型的半导体材料的主体区域，在体区内具有第二导电类型的半导体材料的源极区域，具有第二导电类型的半导体材料的结隔离区域，漏极区域 具有第二导电类型的半导体材料以及具有第二导电类型的半导体材料的第一和第二漂移区。 第一漂移区域横向地位于漏极区域和结隔离区域之间，结隔离区域横向位于第一漂移区域和第二漂移区域之间，并且第二漂移区域横向居住在体区域和结隔离区域之间。

公开(公告)号：US09508845B1

公开(公告)日：2016-11-29

申请号：US14822122

申请日：2015-08-10

Applicant: Freescale Semiconductor, Inc.

Inventor： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/66659 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7835

Abstract: An LDMOS device implements a substrate having a buried isolation layer, a first well region that incorporates two stacked sub-regions to provide a PN junction with a RESURF effect, and a second well region laterally offset from the first well region. A source region is formed in one of the well regions and a drain region is formed in the other well region. An extension region is disposed immediately adjacent to the first well region and laterally distal to the second well region. An extension biasing region is formed at least partially within the extension region, and is separated from the first well region by a portion of the extension region. One or more metallization structures electrically couple the extension biasing region to the one of the source/drain region in the second well region. A gate structure at least partially overlaps both well regions.

Abstract translation: LDMOS器件实现具有掩埋隔离层的衬底，第一阱区域，其结合两个堆叠的子区域以提供具有RESURF效应的PN结，以及从第一阱区域横向偏移的第二阱区域。 在一个阱区中形成源极区，在另一个阱区中形成漏极区。 延伸区域紧邻第一井区域并且横向于第二井区域的横向设置。 延伸偏置区域至少部分地形成在延伸区域内，并且通过延伸区域的一部分与第一阱区域分离。 一个或多个金属化结构将延伸偏置区域电耦合到第二阱区域中的源极/漏极区域中的一个。 门结构至少部分地重叠两个阱区。

公开(公告)号：US20170077295A1

公开(公告)日：2017-03-16

申请号：US14851360

申请日：2015-09-11

Applicant: Freescale Semiconductor, Inc.

Inventor： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L21/266 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76224 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.

Abstract translation: 一种器件包括半导体衬底，设置在半导体衬底中并且限定掺杂隔离栅内的核心器件区域的掺杂隔离栅;隔离接触区域，设置在芯体器件区域外部的半导体衬底中，施加电压 以及设置在芯体装置区域外的半导体基板中的耗尽阱区域。 耗尽的阱区电耦合隔离接触区域和掺杂的隔离栅极，使得掺杂的隔离栅极被偏置在低于施加到隔离接触区域的电压的电压电平。

公开(公告)号：US09040384B2

公开(公告)日：2015-05-26

申请号：US13656122

申请日：2012-10-19

Applicant: Freescale Semiconductor, Inc.

Inventor： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC: H01L21/76 ,  H01L21/331 ,  H01L29/861 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/063 ,  H01L27/1207 ,  H01L29/0692 ,  H01L29/66204 ,  H01L29/861

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

Abstract translation: 提供了沟槽隔离的RESURF二极管结构（100），其包括衬底（150），其中形成阳极（130,132）和阴极（131）接触区域，所述接触区域由浅沟槽隔离区域（114,115） ）以及在阳极接触区域（130,132）下限定垂直和水平pn结的不均匀阴极区（104）和外围阳极区（106,107），其包括被屏蔽的水平阴极/阳极结 通过重掺杂的阳极接触区域（132）。