公开(公告)号：US09059176B2

公开(公告)日：2015-06-16

申请号：US13451947

申请日：2012-04-20

申请人： Frieder Hainrich Baumann ,  Chao-Kun Hu ,  Andrew H. Simon ,  Tibor Bolom ,  Koichi Motoyama ,  Chengyu Charles Niu

发明人： Frieder Hainrich Baumann ,  Chao-Kun Hu ,  Andrew H. Simon ,  Tibor Bolom ,  Koichi Motoyama ,  Chengyu Charles Niu

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

摘要翻译： 具有位于邻近侧壁的扩散阻挡层的结构和在介电材料层中蚀刻的开口的底部。 该结构还具有直接位于扩散阻挡层顶部的金属衬垫，直接位于金属衬垫顶部上的种子层，其中种子层由包括铜的材料制成，铜材料直接位于种子顶部 层，直接位于铜材料的顶部和选择性上的金属盖，以及直接位于金属盖的顶部并且邻近金属盖的封盖层。

公开(公告)号：US20130277842A1

公开(公告)日：2013-10-24

申请号：US13451947

申请日：2012-04-20

申请人： Frieder Hainrich Baumann ,  Chao-Kun Hu ,  Andrew H. Simon ,  Tibor Bolom ,  Koichi Motoyama ,  Chengyu Charles Niu

发明人： Frieder Hainrich Baumann ,  Chao-Kun Hu ,  Andrew H. Simon ,  Tibor Bolom ,  Koichi Motoyama ,  Chengyu Charles Niu

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

公开(公告)号：US07671362B2

公开(公告)日：2010-03-02

申请号：US11953568

申请日：2007-12-10

申请人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

发明人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

IPC分类号： H01L23/58

CPC分类号： H01L22/12 ,  H01L22/34

摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

摘要翻译： 集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化， 相同的沉积工艺条件。

公开(公告)号：US20090146143A1

公开(公告)日：2009-06-11

申请号：US11953568

申请日：2007-12-10

申请人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

发明人： Tibor Bolom ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Paul S. McLaughlin ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert ,  James Werking

IPC分类号： H01L23/58 ,  H01L21/4763

CPC分类号： H01L22/12 ,  H01L22/34

摘要： A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

摘要翻译： 集成电路（IC）器件制造的测试结构包括形成在IC晶片的各个区域的多个测试结构链，所述多个测试结构链中的每一个包括一个或多个通孔; 所述一个或多个通孔中的每一个与设置在其上的导电线接触，所述导电线被配置为使得其至少一个尺寸从链到链变化，从而在种子层和衬层层厚度之间产生从链到链的变化， 相同的沉积工艺条件。

公开(公告)号：US06975032B2

公开(公告)日：2005-12-13

申请号：US10319967

申请日：2002-12-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

公开(公告)号：US07064064B2

公开(公告)日：2006-06-20

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US08232646B2

公开(公告)日：2012-07-31

申请号：US12691213

申请日：2010-01-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.

摘要翻译： 用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分 。

公开(公告)号：US06399496B1

公开(公告)日：2002-06-04

申请号：US09714504

申请日：2000-11-16

申请人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

发明人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.

摘要翻译： 本发明公开了一种用于与电子设备进行电连接的互连结构，该电子设备包括基本上由铜形成的主体和不包含铜的铜合金或金属的籽晶层夹在铜导体本体和 用于提高互连结构的电迁移电阻，粘附性等表面性质的电子器件。 本发明还公开了用于形成互连结构的方法，该互连结构用于通过首先在电子器件上沉积铜合金或不含铜的其它金属的种子层，然后在其上形成铜导体，从而提供与电子器件的电连接 种子层紧密地结合到层上，使得互连结构的电迁移阻力，粘附性和其它表面性质得到改善。

公开(公告)号：US08056039B2

公开(公告)日：2011-11-08

申请号：US12128973

申请日：2008-05-29

申请人： Kaushik Chanda ,  Ronald Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

发明人： Kaushik Chanda ,  Ronald Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

IPC分类号： G06F17/50

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.

摘要翻译： 用于集成电路（IC）装置的互连结构包括细长的导电线，其包括形成在第一宽度w 1处的一个或多个段以及以一个或多个附加宽度w2形成的一个或多个段。 。 。 wN，其中第一宽度比一个或多个附加宽度中的每一个窄; 其中形成在第一宽度处的一个或多个导电段的总长度L1与总长度L2的关系。 。 。 选择以一个或多个附加宽度形成的一个或多个导电段的LN，使得对于给定的导电线承载的电流，相对于电迁移短长度效应益处的临界长度被保​​持为 导线的总长度L = L1 + L2 +。 。 。 + LN，无论临界长度如何，满足最小设计长度。

公开(公告)号：US20090294901A1

公开(公告)日：2009-12-03

申请号：US12132337

申请日：2008-06-03

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

IPC分类号： H01L21/768 ,  H01L23/58

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.

摘要翻译： 用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。