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    CMOS millimeter-wave variable-gain low-noise amplifier
    2.
    发明授权
    CMOS millimeter-wave variable-gain low-noise amplifier 有权
    CMOS毫米波可变增益低噪声放大器

    公开(公告)号：US08279008B2

    公开(公告)日：2012-10-02

    申请号：US12851705

    申请日：2010-08-06

    申请人： Hsieh-Hung Hsieh ,  Po-Yi Wu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Po-Yi Wu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03G3/30 ,  H03F1/22 ,  H03F3/16

    CPC分类号： H03G1/0029 ,  H03F1/223 ,  H03F3/195 ,  H03F2200/249 ,  H03F2200/318 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/492 ,  H03G3/3052

    摘要： A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal.

    摘要翻译： 低噪声放大器（LNA）包括耦合到输入节点的第一共源共同增益级，用于增加RF输入信号的幅度。 第一可变增益网络耦合到第一共源共同增益级，并且包括用于升高第一共源共享增益级的增益的第一电感器，耦合到第一电感器以阻止直流（DC）电压的第一电容器，以及第一可变增益网络 开关耦合到第一电感器和第一电容器。 第一开关被配置为响应于第一控制信号选择性地将第一电感器耦合到第一共源共享增益级。

    DIVIDER-LESS PHASE LOCKED LOOP (PLL)
    4.
    发明申请
    DIVIDER-LESS PHASE LOCKED LOOP (PLL) 有权
    无相位锁相环（PLL）

    公开(公告)号：US20140049329A1

    公开(公告)日：2014-02-20

    申请号：US13586033

    申请日：2012-08-15

    申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

    发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

    IPC分类号： H03L7/099

    CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

    摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

    摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。

    Method and apparatus for amplifying a time difference
    5.
    发明授权
    Method and apparatus for amplifying a time difference 有权
    用于放大时差的方法和装置

    公开(公告)号：US08476972B2

    公开(公告)日：2013-07-02

    申请号：US12813620

    申请日：2010-06-11

    申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： G06G7/12 ,  G06G7/26

    CPC分类号： G04F10/005

    摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

    摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

    ESD protection circuit for RFID tag
    6.
    发明授权
    ESD protection circuit for RFID tag 有权
    RFID标签的ESD保护电路

    公开(公告)号：US08324658B2

    公开(公告)日：2012-12-04

    申请号：US12759743

    申请日：2010-04-14

    申请人： Ming-Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Ming-Hsiang Song

    发明人： Ming-Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Ming-Hsiang Song

    IPC分类号： H01L29/73

    CPC分类号： H01L29/73

    摘要： An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively.

    摘要翻译： 静电放电（ESD）保护电路结构包括形成在衬底中的双向可控硅整流器（SCR）。 SCR包括由N阱横向插入的第一和第二P阱。 深井N井位于P井和N井的下面。 第一和第二N型区域分别设置在第一和第二P阱中，并且耦合到一对焊盘。 第一和第二P型区域分别设置在第一和第二P阱中，分别耦合到焊盘，并且分别设置成比第一和第二N型区域更靠近N阱。

    Built-in Self-test Circuit for Voltage Controlled Oscillators
    7.
    发明申请
    Built-in Self-test Circuit for Voltage Controlled Oscillators 有权
    用于压控振荡器的内置自检电路

    公开(公告)号：US20120286836A1

    公开(公告)日：2012-11-15

    申请号：US13103571

    申请日：2011-05-09

    申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03K3/84

    CPC分类号： G01R31/2824

    摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

    摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

    Low-noise amplifier with gain enhancement
    8.
    发明授权
    Low-noise amplifier with gain enhancement 有权
    具有增益增益的低噪声放大器

    公开(公告)号：US08427240B2

    公开(公告)日：2013-04-23

    申请号：US12968342

    申请日：2010-12-15

    申请人： Hsieh-Hung Hsieh ,  Po-Yi Wu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Po-Yi Wu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03F3/04

    CPC分类号： H03G1/0029 ,  H03F1/223 ,  H03F3/195 ,  H03F2200/249 ,  H03F2200/318 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/492

    摘要： A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.

    摘要翻译： 低噪声放大器（“LNA”）包括第一共源共栅增益级，其包括被配置为接收射频（“RF”）输入信号的第一互补金属氧化物半导体（“CMOS”）晶体管和耦合到 输出节点。 第一感应栅极网络耦合到第二CMOS晶体管的栅极，用于增加第一共源共栅增益级的增益。 第一感应栅极网络具有非零电感输入阻抗并且包括至少一个无源电路元件。

    Switched Capacitor Array for Voltage Controlled Oscillator
    9.
    发明申请
    Switched Capacitor Array for Voltage Controlled Oscillator 审中-公开
    用于压控振荡器的开关电容阵列

    公开(公告)号：US20120286888A1

    公开(公告)日：2012-11-15

    申请号：US13103592

    申请日：2011-05-09

    申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03B5/12 ,  H03H11/00

    CPC分类号： H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/0266

    摘要： A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code.

    摘要翻译： 一种系统包括压控振荡器，其包括电感器和可变电容器以及与可变电容器并联连接的开关电容器阵列。 开关电容器阵列还包括多个电容器组，其中使用温度计代码来控制每个电容器组。 此外，当开关电容器阵列由n位温度计代码控制时，开关电容器阵列为压控振荡器的振荡频率提供N个调谐步骤。

    Capacitor coupled quadrature voltage controlled oscillator
    10.
    发明授权
    Capacitor coupled quadrature voltage controlled oscillator 有权
    电容耦合正交压控振荡器

    公开(公告)号：US08258879B2

    公开(公告)日：2012-09-04

    申请号：US12907294

    申请日：2010-10-19

    申请人： Ying-Ta Lu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： Ying-Ta Lu ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： H03L7/00

    CPC分类号： H03B27/00 ,  H03B5/1215 ,  H03B5/1228

    摘要： A quadrature oscillator includes a first oscillator having a first second-order harmonic node, a second oscillator having a second second-order harmonic node, and at least one capacitor coupling the first second-order harmonic node and the second second-order harmonic node. The first oscillator is configured to supply an in-phase signal and the second oscillator is configured to supply a quadrature signal.

    摘要翻译： 正交振荡器包括具有第一二次谐波节点的第一振荡器，具有第二二次谐波节点的第二振荡器和耦合第一二次谐波节点和第二二次谐波节点的至少一个电容器。 第一振荡器被配置为提供同相信号，并且第二振荡器被配置为提供正交信号。