公开(公告)号：US5684729A

公开(公告)日：1997-11-04

申请号：US530471

申请日：1995-09-19

申请人： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hideo Sawamoto ,  Takahiro Nishiyama ,  Yoshikazu Kiyoshige ,  Noriyasu Ido

发明人： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hideo Sawamoto ,  Takahiro Nishiyama ,  Yoshikazu Kiyoshige ,  Noriyasu Ido

IPC分类号： G06F7/50 ,  G06F7/74

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49947 ,  G06F7/49994

摘要： To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.

摘要翻译： 为了提供能够缩短计算时间的浮点加法/减法处理装置及其方法，浮点计算处理装置包括：近似移位预测单元，用于通过使用输入浮点运算处理装置预测用于归一化的移位量， 点数据在1比特的误差内进行加法/减法处理;移位误差检测单元，用于检测预测偏移量和正确移位量之间的差;以及位移移位器，用于校正结果， 移位量乘以检测到的两个移动量的差异，其中在执行归一化移位处理之前并行处理舍入确定和移位量计算。

公开(公告)号：US5841300A

公开(公告)日：1998-11-24

申请号：US838193

申请日：1997-04-16

申请人： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hiromichi Yamada

发明人： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hiromichi Yamada

IPC分类号： H03K19/003 ,  H03K19/096

CPC分类号： H03K19/00338

摘要： The present invention is intended to provide a conventional circuit apparatus which is highly tolerant to noises and operates at a higher speed than a completely complementary static CMOS circuit. To achieve this, circuit apparatus according to the present invention is provided with a plurality of CMOS static logic circuits which are series-connected and potential setting means which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore circuit operation is speeded up and .alpha. particle noise and noises due to charge redistribution effect or leakage current can be prevented.

摘要翻译： 本发明旨在提供一种传统的电路设备，其高度耐受噪声并且以比完全互补的静态CMOS电路更高的速度工作。 为了实现这一点，根据本发明的电路装置设置有多个串联的CMOS静态逻辑电路和电位设置装置，其连接到这些逻辑电路的输出部分并将输出部分的输出设置为 与时钟信号同步的低电平，从而通过NMOS电路的操作来传播信号。 换句话说，信号传播延迟仅在N型逻辑块导通时才发生。 因此，电路操作加快，可以防止由于电荷再分配效应或漏电流引起的α粒子噪声和噪声。

公开(公告)号：US06590425B2

公开(公告)日：2003-07-08

申请号：US09887065

申请日：2001-06-25

申请人： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hiromichi Yamada

发明人： Fumio Murabayashi ,  Tatsumi Yamauchi ,  Takashi Hotta ,  Hiromichi Yamada

IPC分类号： H03K19096

CPC分类号： H03K19/00338

摘要： There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented. There is also disclosed a parallel data processing apparatus which features such logic circuitry, the data processing apparatus having both a plurality of data processing units, each having a processor and a memory, and a plurality of hard disks.

摘要翻译： 公开了一种电路装置，其高度耐受噪声并以比传统的完全互补的静态CMOS电路更高的速度工作。 为了实现这一点，电路装置具有串联连接的多个CMOS静态逻辑电路和连接到这些逻辑电路的输出部分的电位设置电路，并将输出部分的输出与 时钟信号，从而通过NMOS电路的操作传播信号。 换句话说，信号传播延迟仅在N型逻辑块导通时才发生。 因此，可以防止电路操作加剧，并且可以防止由于电荷再分配效应或漏电流引起的α粒子噪声和噪声。 还公开了一种具有这种逻辑电路的并行数据处理装置，数据处理装置具有多个数据处理单元，每个数据处理单元具有处理器和存储器，以及多个硬盘。

公开(公告)号：US06539322B1

公开(公告)日：2003-03-25

申请号：US09583770

申请日：2000-05-31

申请人： Masahiro Matsumoto ,  Kohei Sakurai ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Tatsumi Yamauchi ,  Atsushi Miyazaki ,  Keiji Hanzawa

发明人： Masahiro Matsumoto ,  Kohei Sakurai ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Tatsumi Yamauchi ,  Atsushi Miyazaki ,  Keiji Hanzawa

IPC分类号： G06M1102

CPC分类号： G01D3/08 ,  G01D3/022 ,  Y10T436/11

摘要： A sensor device is provided which included a digital arithmetic processing unit which performs arithmetic processing through a program stored therein in advance, a pulse generator for generating pulses through the program, and a unit for causing the output voltage of the sensor device to stay at either a power source voltage concerned or the ground voltage, when the pulses from the pulse generator are interrupted, thereby, a sensor device using digital arithmetic processing and outputting analogue voltages is provided allowing the host system to judge easily whether the sensor device is operating normally or is failing.

摘要翻译： 提供了一种传感器装置，其包括：数字运算处理单元，其预先通过存储在其中的程序执行算术处理;脉冲发生器，用于通过程序产生脉冲;以及单元，用于使传感器装置的输出电压停留在任一个 当来自脉冲发生器的脉冲被中断时，提供有关的电源电压或接地电压，由此提供使用数字运算处理和输出模拟电压的传感器装置，允许主机系统容易地判断传感器装置是否正常运行，或者 失败了

公开(公告)号：US5677641A

公开(公告)日：1997-10-14

申请号：US423378

申请日：1995-04-18

申请人： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

发明人： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

IPC分类号： G11C11/41 ,  H03K3/3565 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K3/3565 ,  H03K19/018521

摘要： The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.

摘要翻译： 本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低幅度以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流 尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。 当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极 通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

公开(公告)号：US06538866B1

公开(公告)日：2003-03-25

申请号：US09526737

申请日：2000-03-16

申请人： Keiji Hanzawa ,  Masahiro Matsumoto ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Hiromichi Yamada ,  Kohei Sakurai ,  Atsushi Miyazaki

发明人： Keiji Hanzawa ,  Masahiro Matsumoto ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Hiromichi Yamada ,  Kohei Sakurai ,  Atsushi Miyazaki

IPC分类号： H02H900

CPC分类号： H01L27/0251 ,  H02H9/04

摘要： A circuit for protecting a load from an overvoltage can be integrated together with the load on the same chip by an MOS transistor manufacture process. This overvoltage protecting circuit is composed of a surge protection circuit, an overvoltage detecting circuit and a switching circuit. The surge protection circuit including two MOS transistors operates so that a surge voltage applied to a power supply receiving terminal is clamped by virtue of the source-drain breakdown voltage of the two MOS transistors, thereby absorbing the surge energy. The overvoltage detecting circuit including two MOS transistors operates so that a DC voltage supplied from the surge protection circuit is monitored with the source-drain voltage of the two MOS transistors taken as a reference voltage, thereby detecting an overvoltage. An overvoltage detection output brings an MOS transistor of the switching circuit into a turned-off condition to protect the load.

摘要翻译： 可以通过MOS晶体管制造工艺将用于保护负载的过电压的电路与负载集成在同一芯片上。 该过电压保护电路由浪涌保护电路，过电压检测电路和开关电路构成。 包括两个MOS晶体管的浪涌保护电路工作，借助于两个MOS晶体管的源极 - 漏极击穿电压来钳位施加到电源接收端的浪涌电压，从而吸收浪涌能量。 包括两个MOS晶体管的过电压检测电路进行工作，从而以两个MOS晶体管的源极 - 漏极电压作为参考电压来监视从浪涌保护电路提供的直流电压，从而检测过电压。 过电压检测输出使开关电路的MOS晶体管成为关断状态，以保护负载。

公开(公告)号：US06657459B2

公开(公告)日：2003-12-02

申请号：US10143762

申请日：2002-05-14

申请人： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

发明人： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

IPC分类号： H03K19096

CPC分类号： H03K3/3565 ,  H03K19/018521

摘要： A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

公开(公告)号：US5931895A

公开(公告)日：1999-08-03

申请号：US789430

申请日：1997-01-29

申请人： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Noriyasu Ido ,  Yoshikazu Kiyoshige ,  Takahiro Nishiyama ,  Eiki Kamada

发明人： Hiromichi Yamada ,  Fumio Murabayashi ,  Tatsumi Yamauchi ,  Noriyasu Ido ,  Yoshikazu Kiyoshige ,  Takahiro Nishiyama ,  Eiki Kamada

IPC分类号： G06F7/38 ,  G06F5/01 ,  G06F7/00 ,  G06F7/483 ,  G06F7/74 ,  G06F7/76 ,  G06F7/52

CPC分类号： G06F5/012 ,  G06F7/483

摘要： A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.

摘要翻译： 一种浮点运算处理装置，具有通过从中间结果的指数的值减去归一化数的最小值的指数来生成用于归一化偏移的极限值的电路，以及生成作为归一化的归一化的电路 移位数，使中间结果的尾数所需的移位数中的较小的一个是归一化数，以及归一化移位的极限值。 浮点运算处理装置还具有电路，该电路具有用于检测在舍入处理之前的溢出条件的电路和用于在溢出的情况下产生值的电路，从而仅当预定值仅在 在舍入处理之前检测到溢出条件，但是在另一种情况下，通过执行归一化处理和舍入处理获得的结果被传送。 在四舍五入处理之前没有发生溢出，而在舍入处理后发生溢出的情况下，通过执行归一化处理和舍入处理获得的结果作为最终结果被传递。

公开(公告)号：US06462580B2

公开(公告)日：2002-10-08

申请号：US09749474

申请日：2000-12-28

申请人： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

发明人： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

IPC分类号： H03K19096

CPC分类号： H03K3/3565 ,  H03K19/018521

摘要： The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.

摘要翻译： 本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低振幅以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流， 尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。 当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极 通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

公开(公告)号：US06282136B1

公开(公告)日：2001-08-28

申请号：US09578854

申请日：2000-05-26

申请人： Kohei Sakurai ,  Tatsumi Yamauchi ,  Masahiro Matsumoto ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Atsushi Miyazaki ,  Keiji Hanzawa

发明人： Kohei Sakurai ,  Tatsumi Yamauchi ,  Masahiro Matsumoto ,  Fumio Murabayashi ,  Hiromichi Yamada ,  Atsushi Miyazaki ,  Keiji Hanzawa

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/12 ,  G11C8/00

摘要： In a semiconductor memory device, the drain of a transistor for pre-charging is connected to a data line via the Y switch. Lower level bit signals are input into an X decoder for selecting the word line in a memory cell array; and higher level bit signals are input into a Y decoder for selecting the Y switch control signal lines. The addresses in the memory cell array are arranged sequentially in the direction of the data lines.

摘要翻译： 在半导体存储器件中，用于预充电的晶体管的漏极经由Y开关连接到数据线。 低电平位信号被输入到用于选择存储单元阵列中的字线的X解码器中; 并且较高电平位信号被输入到用于选择Y开关控制信号线的Y解码器中。 存储单元阵列中的地址在数据线的方向上顺序排列。