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    INTELLIGENT MEMORY ARCHITECTURE FOR INCREASED EFFICIENCY
    1.
    发明申请
    INTELLIGENT MEMORY ARCHITECTURE FOR INCREASED EFFICIENCY 审中-公开
    提高效率的智能记忆体系结构

    公开(公告)号：US20170031619A1

    公开(公告)日：2017-02-02

    申请号：US14810895

    申请日：2015-07-28

    申请人： Futurewei Technologies, Inc.

    发明人： Hao Luan ,  Alan Gatherer ,  Sriram Vishwanath ,  Casen Hunger ,  Hardik Jain

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0622 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0688

    摘要： A method includes receiving a first request, from a first master core, to access data in one of a plurality of memory banks. It is determined whether an access to the data is stalled by virtue of a second request, from a second master core, to access the data in the one of the plurality of memory banks, the second request currently being serviced. In response to a determination that the access to the requested data is stalled, the first request is serviced by accessing data in one of a plurality of coding banks, each coding bank smaller in size than each memory bank.

    摘要翻译： 一种方法包括从第一主核心接收第一请求以访问多个存储器组之一中的数据。 确定通过第二请求从第二主核心访问对数据的访问是否访问多个存储体中的一个存储器中的数据，当前正在服务的第二请求。 响应于对所请求数据的访问被停止的确定，通过访问多个编码组之一中的数据来服务第一请求，每个编码组的尺寸小于每个存储体。

    Intelligent memory architecture for increased efficiency
    3.
    发明授权
    Intelligent memory architecture for increased efficiency 有权

    公开(公告)号：US10180803B2

    公开(公告)日：2019-01-15

    申请号：US14810895

    申请日：2015-07-28

    申请人： Futurewei Technologies, Inc.

    发明人： Hao Luan ,  Alan Gatherer ,  Sriram Vishwanath ,  Casen Hunger ,  Hardik Jain

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F3/06

    摘要： A method includes receiving a first request, from a first master core, to access data in one of a plurality of memory banks. It is determined whether an access to the data is stalled by virtue of a second request, from a second master core, to access the data in the one of the plurality of memory banks, the second request currently being serviced. In response to a determination that the access to the requested data is stalled, the first request is serviced by accessing data in one of a plurality of coding banks, each coding bank smaller in size than each memory bank.

    Intelligent coded memory architecture with enhanced access scheduler
    6.
    发明授权
    Intelligent coded memory architecture with enhanced access scheduler 有权

    公开(公告)号：US10437480B2

    公开(公告)日：2019-10-08

    申请号：US14955966

    申请日：2015-12-01

    申请人： Futurewei Technologies, Inc.

    发明人： Hao Luan ,  Alan Gatherer ,  Sriram Vishwanath ,  Casen Hunger ,  Hardik Jain

    IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F11/10

    摘要： A method, system, and architecture for efficiently accessing data in a memory shared by multiple processor cores that reduces the probability of bank conflicts and decreases latency is provided. In an embodiment, a method for accessing data in a memory includes determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks; reading a first data from a first memory bank; reading coded data from one of the coding banks; and determining the second data according to the coded data and the first data.