公开(公告)号：US20160308073A1

公开(公告)日：2016-10-20

申请号：US14687549

申请日：2015-04-15

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/10

CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L29/1095 ,  H01L29/66189 ,  H01L29/94

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

Abstract translation: 本文提供了用于低损耗耦合电容器结构的实施例。 这些实施例包括n型变容二极管（NVAR）配置和p型变容二极管（PVAR）配置。 NVAR配置中的结构包括Pub掺杂半导体衬底（Psub），Psub中的深n掺杂半导体阱（DNW）和DNW中的p掺杂半导体阱（P阱）。 电路结构还包括P阱内的p掺杂半导体材料的源极端子和P阱内的p掺杂半导体材料的漏极端子。 另外，电路结构包括在P阱的表面上的绝缘栅极，包括多层金属线的金属图案，以及穿过金属线的多个通孔。 通孔是将金属线连接到栅极，源极端子和漏极端子的触点。

公开(公告)号：US20200321479A1

公开(公告)日：2020-10-08

申请号：US16813702

申请日：2020-03-09

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence E. Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/94 ,  H01L27/08 ,  H01L29/10

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US10586878B2

公开(公告)日：2020-03-10

申请号：US15830927

申请日：2017-12-04

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/94 ,  H01L29/66 ,  H01L29/10 ,  H01L27/08

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US20180090627A1

公开(公告)日：2018-03-29

申请号：US15830927

申请日：2017-12-04

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/94 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L29/1095 ,  H01L29/66189 ,  H01L29/94

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US09837555B2

公开(公告)日：2017-12-05

申请号：US14687549

申请日：2015-04-15

Applicant: Futurewei Technologies, Inc.

Inventor： Brian Creed ,  Lawrence Connell ,  Kent Jaeger ,  Matthew Richard Miller

IPC: H01L29/93 ,  H01L29/10 ,  H01L29/68 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L29/1095 ,  H01L29/66189 ,  H01L29/94

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

公开(公告)号：US09729126B2

公开(公告)日：2017-08-08

申请号：US14925799

申请日：2015-10-28

Applicant: Futurewei Technologies, Inc.

Inventor： Homero Luz Guimaraes ,  Matthew Richard Miller

IPC: H03F3/04 ,  G06G7/12 ,  H03H11/12 ,  H03F3/193 ,  H03F1/02 ,  H03F3/45

CPC classification number: H03F1/0205 ,  H03F1/086 ,  H03F3/193 ,  H03F3/3022 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45511 ,  H03F2200/451 ,  H03H11/1256

Abstract: Method and implementation of gain-bandwidth product (GWB) tuning are disclosed. In an embodiment an operational amplifier (opamp) includes an input stage of the opamp including a differential device pair coupled to a tail device and configured to be responsive to a differential input signal for conducting a first current and an output stage of the opamp including a class AB interface stage circuit and a pair of output devices connected to the class AB interface stage circuit, wherein a first constant gm bias circuit is coupled to an input terminal of the class AB interface stage circuit.

公开(公告)号：US08928407B2

公开(公告)日：2015-01-06

申请号：US13794442

申请日：2013-03-11

Applicant: Futurewei Technologies, Inc.

Inventor： Matthew Richard Miller ,  Terrie McCain

IPC: H03F3/45 ,  H03G3/00

CPC classification number: H03F3/45179 ,  H03F2200/91 ,  H03F2203/45306 ,  H03F2203/45318 ,  H03G1/0029 ,  H03G3/00 ,  H03G3/3068

Abstract: A system includes a first variable gain amplifier configured to receive an input signal and a first down-mixer coupled to the first variable gain amplifier. Also, the system includes a first current conveyor coupled to the first down mixer, where the first current conveyor includes a first cascode and a second cascode coupled to the first cascode. Additionally, the system includes a first channel filter coupled to the first current conveyor and a second variable gain amplifier coupled to the first channel filter.

Abstract translation: 系统包括被配置为接收输入信号的第一可变增益放大器和耦合到第一可变增益放大器的第一下混频器。 而且，该系统包括耦合到第一下混合器的第一电流输送器，其中第一电流输送器包括第一共源共栅和耦合到第一共源共栅的第二共源共栅。 另外，该系统包括耦合到第一电流传输器的第一通道滤波器和耦合到第一通道滤波器的第二可变增益放大器。

公开(公告)号：US10771028B2

公开(公告)日：2020-09-08

申请号：US16172507

申请日：2018-10-26

Applicant: Futurewei Technologies, Inc.

Inventor： William Roeckner ,  Terrie McCain ,  Matthew Richard Miller ,  Lawrence E. Connell

IPC: H03F1/02 ,  H03F3/45 ,  H03G1/00 ,  H03F3/00

Abstract: An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.

公开(公告)号：US20170126207A1

公开(公告)日：2017-05-04

申请号：US14925799

申请日：2015-10-28

Applicant: Futurewei Technologies, Inc.

Inventor： Homero Luz Guimaraes ,  Matthew Richard Miller

IPC: H03H11/12 ,  H03F1/02 ,  H03F3/45 ,  H03F3/193

CPC classification number: H03F1/0205 ,  H03F1/086 ,  H03F3/193 ,  H03F3/3022 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45511 ,  H03F2200/451 ,  H03H11/1256

Abstract: Method and implementation of gain-bandwidth product (GWB) tuning are disclosed. In an embodiment an operational amplifier (opamp) includes an input stage of the opamp including a differential device pair coupled to a tail device and configured to be responsive to a differential input signal for conducting a first current and an output stage of the opamp including a class AB interface stage circuit and a pair of output devices connected to the class AB interface stage circuit, wherein a first constant gm bias circuit is coupled to an input terminal of the class AB interface stage circuit.

公开(公告)号：US08952748B2

公开(公告)日：2015-02-10

申请号：US13872727

申请日：2013-04-29

Applicant: FutureWei Technologies, Inc.

Inventor： Homero Guimaraes ,  Matthew Richard Miller

IPC: H03K17/16 ,  H03K17/687 ,  H01L29/92 ,  G08C19/00 ,  H01L49/02

CPC classification number: G08C19/00 ,  H01L27/0805 ,  H01L28/40 ,  H01L29/94

Abstract: An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.

Abstract translation: 实施例集成电路包括第一电容元件，其包括与第一电容元件并联耦合的第一金属氧化物半导体（MOS）电容器和第二电容元件，其中第二电容元件包括第二MOS电容器。 此外，集成电路包括与第一电容元件和第二电容元件并联耦合的第三电容元件，其中第三电容元件包括第一金属 - 绝缘体金属（MIM）电容器和与第 第一电容元件，第二电容元件和第三电容元件，其中第四电容元件包括第二MIM电容器。