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    GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH ROBUST INNER SPACERS AND METHODS
    1.
    发明申请
    GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH ROBUST INNER SPACERS AND METHODS 有权

    公开(公告)号：US20210043727A1

    公开(公告)日：2021-02-11

    申请号：US16534317

    申请日：2019-08-07

    申请人： GLOBALFOUNDRIES INC.

    发明人： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

    IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

    摘要： A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

    AIRGAP SPACERS FORMED IN CONJUNCTION WITH A LATE GATE CUT
    2.
    发明申请
    AIRGAP SPACERS FORMED IN CONJUNCTION WITH A LATE GATE CUT 审中-公开

    公开(公告)号：US20200152504A1

    公开(公告)日：2020-05-14

    申请号：US16185799

    申请日：2018-11-09

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

    IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L29/49

    摘要： Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.

    Stacked nanosheet field-effect transistor with air gap spacers
    5.
    发明授权
    Stacked nanosheet field-effect transistor with air gap spacers 有权

    公开(公告)号：US10269983B2

    公开(公告)日：2019-04-23

    申请号：US15590409

    申请日：2017-05-09

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Julien Frougier ,  Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L29/41

    摘要： Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.

    METHODS OF FORMING A GATE CONTACT STRUCTURE FOR A TRANSISTOR
    6.
    发明申请
    METHODS OF FORMING A GATE CONTACT STRUCTURE FOR A TRANSISTOR 审中-公开

    公开(公告)号：US20190096677A1

    公开(公告)日：2019-03-28

    申请号：US15712301

    申请日：2017-09-22

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-Chen Yeh

    IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

    摘要： One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.

    INTEGRATED CIRCUIT STRUCTURE HAVING VFET AND EMBEDDED MEMORY STRUCTURE AND METHOD OF FORMING SAME
    7.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE HAVING VFET AND EMBEDDED MEMORY STRUCTURE AND METHOD OF FORMING SAME 审中-公开

    公开(公告)号：US20190051659A1

    公开(公告)日：2019-02-14

    申请号：US15673548

    申请日：2017-08-10

    申请人： GLOBALFOUNDRIES INC.

    发明人： Ruilong Xie ,  Chun-Chen Yeh ,  Tenko Yamashita ,  Kangguo Cheng

    IPC分类号： H01L27/11556 ,  H01L27/11526

    摘要： The disclosure is directed to an integrated circuit structure and method of forming the same. The integrated circuit structure may include: a first device region including: a floating gate structure substantially surrounding a first fin that is over a substrate; a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure; a first top source/drain over the first fin and the floating gate structure; a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate.