公开(公告)号：US20190043956A1

公开(公告)日：2019-02-07

申请号：US16018304

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/16 ,  H01L21/02

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

公开(公告)号：US09972620B2

公开(公告)日：2018-05-15

申请号：US15234762

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charan V. Surisetty ,  Dominic J. Schepis ,  Kangguo Cheng ,  Alexander Reznicek

IPC: H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791

Abstract: Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.

公开(公告)号：US09966374B2

公开(公告)日：2018-05-08

申请号：US15096681

申请日：2016-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Charan Veera Venkata Satya Surisetty

IPC: H01L29/51 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L27/0886 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/41766 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.

公开(公告)号：US20170301697A1

公开(公告)日：2017-10-19

申请号：US15098722

申请日：2016-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Veeraraghavan S. Basker ,  Shogo Mochizuki ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/324 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02623 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/01 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/7848

Abstract: Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed.The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.

公开(公告)号：US09754941B2

公开(公告)日：2017-09-05

申请号：US14729845

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/18 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L29/161

CPC classification number: H01L27/0924 ,  H01L21/18 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.

公开(公告)号：US09728649B2

公开(公告)日：2017-08-08

申请号：US15009906

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/786 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

公开(公告)号：US09673296B2

公开(公告)日：2017-06-06

申请号：US14937029

申请日：2015-11-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

IPC: H01L29/76 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/84 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/78

Abstract: A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.

公开(公告)号：US20160358922A1

公开(公告)日：2016-12-08

申请号：US14729845

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/18 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.

Abstract translation: 提供一种形成半导体结构的方法，其包括具有第一锗含量的压缩应变硅锗合金翅片和具有小于第一锗含量的第二锗含量的拉伸应变硅锗合金翅片。 不同的应变和锗含量的硅锗合金翅片位于同一基板上。 该方法包括在一组硅锗合金翅片周围形成硅包覆层，并且在另一组硅锗合金翅片周围形成含锗材料包层。 然后使用热混合形成不同的应变和锗含量的硅锗合金翅片。

公开(公告)号：US20160343623A1

公开(公告)日：2016-11-24

申请号：US14718760

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract translation: 通过使用掺杂氧化物的体积FinFET结构形成穿通停止层。 通过退火将掺杂剂驱入散热片的基板和基部。 穿通停止层包括p型区域和n型区域，它们都可以延伸到半导体鳍片中基本相等的距离。

公开(公告)号：US09385023B1

公开(公告)日：2016-07-05

申请号：US14712462

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joel P. de Souza ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/76 ,  H01L27/12 ,  H01L21/70 ,  H01L21/762 ,  H01L21/225 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/76245 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height that is located on a first buried oxide structure. The structure further includes a second silicon fin of a second height that is located on a second buried oxide structure that is spaced apart from the first buried oxide structure. The second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar of a topmost surface with the second silicon fin.

Abstract translation: 提供了包含具有不同高度的硅散热片的半导体结构，同时为了工艺可行性而保持合理的翅片高宽比。 半导体结构包括位于第一掩埋氧化物结构上的第一高度的第一硅鳍。 该结构还包括第二高度的第二硅片，其位于与第一掩埋氧化物结构间隔开的第二掩埋氧化物结构上。 第二硅片的第二高度大于第一硅片的第一高度，但是第一硅片的最顶面与第二硅片的最顶面共面。