公开(公告)号：US09305800B2

公开(公告)日：2016-04-05

申请号：US14185491

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Tamer Coskun ,  Wei-Long Wang ,  Azat Latypov ,  Yi Zou

IPC: H01L21/308 ,  H01L21/027

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0274 ,  H01L21/308

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成覆盖在半导体衬底上的辅助抗蚀刻填充形貌特征，并且使用光掩模来定义辅助耐蚀刻填充约束阱。 光掩模定义了辅助的可光刻印刷的掩模特征。 将嵌段共聚物沉积到辅助抗蚀填充密封阱中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 辅助抗蚀刻填充形貌特征指示耐腐蚀相以在辅助耐蚀刻填充密封阱中形成耐蚀刻塞。

公开(公告)号：US09009634B2

公开(公告)日：2015-04-14

申请号：US13936910

申请日：2013-07-08

Applicant: GlobalFoundries, Inc.

Inventor： Azat Latypov ,  Yi Zou ,  Vito Dai

IPC: G06F17/50 ,  G03F7/20

CPC classification number: G03F7/70441 ,  B82Y30/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes, using a computing system, inputting a DSA target pattern. Using the computing system, a DSA model, an OPC model, and a MPC model, cooperatively running a DSA PC algorithm, an OPC algorithm, and a MPC algorithm to produce an output MPCed pattern for a mask writer to write on the photomask.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括产生用于在半导体衬底上形成DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括使用计算系统输入DSA目标图案。 使用计算系统，DSA模型，OPC模型和MPC模型，协作运行DSA PC算法，OPC算法和MPC算法，以产生用于掩模写入器在光掩模上写入的输出MPCed模式。

公开(公告)号：US09530662B2

公开(公告)日：2016-12-27

申请号：US14630676

申请日：2015-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Tamer Coskun ,  Moshe Preil

IPC: H01L21/027 ,  H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成多个形貌特征的基本上周期性的阵列，包括多个耐蚀刻的地形特征和至少一个划线斑点特征。 多个耐蚀刻的形貌特征限定了多个耐蚀刻限制孔，并且所述至少一个划线阱特征限定了具有与耐蚀刻限制孔不同的尺寸和/或形状的划线阱限制阱。 将嵌段共聚物沉积到限制孔中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻的地形特征指示耐蚀刻相，在每个耐蚀刻限制孔中形成耐蚀刻塞。

公开(公告)号：US09305834B1

公开(公告)日：2016-04-05

申请号：US14586268

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Ji Xu

IPC: G06F17/50 ,  H01L21/768

CPC classification number: H01L21/76816 ,  G03F7/0002 ,  H01L21/31144

Abstract: Methods for fabricating integrated circuits using directed self-assembly to form via and contact holes are disclosed. An exemplary method includes determining a natural, hexagonal separation distance L0 between cylinders formed in a block copolymer (BCP) material during directed self-assembly (DSA) and determining an integrated circuit feature pitch PA according to the following formula: PA=L0*(sqrt(3)/2)*n, wherein n is a positive integer. The method further includes generating an integrated circuit layout design better accommodating the natural formation arrangement of polymeric cylinders, wherein integrated circuit features are spaced in accordance with the integrated circuit feature pitch PA and wherein via or contact structures are physically and electrically connected to the integrated circuit features and fabricating the integrated circuit features and the via or contact structures on a semiconductor work-in-process (WIP) in accordance with the integrated circuit layout design, wherein the via or contact structures are fabricated utilizing DSA with BCP material.

Abstract translation: 公开了使用定向自组装形成通孔和接触孔的集成电路的制造方法。 示例性方法包括在定向自组装（DSA）期间确定在嵌段共聚物（BCP）材料中形成的气缸之间的天然六边形间隔距离L0，并根据以下公式确定集成电路特征间距PA：PA = L0 *（ sqrt（3）/ 2）* n，其中n是正整数。 该方法还包括生成更好地适应聚合物气瓶的自然形成布置的集成电路布局设计，其中集成电路特征根据集成电路特征间距PA间隔开，并且其中通孔或接触结构物理和电连接到集成电路 特征和制造集成电路特征以及根据集成电路布局设计的半导体工艺（WIP）上的通孔或接触结构，其中通过或接触结构使用具有BCP材料的DSA制造。

公开(公告)号：US20150012896A1

公开(公告)日：2015-01-08

申请号：US13936910

申请日：2013-07-08

Applicant: Globalfoundries, Inc.

Inventor： Azat Latypov ,  Yi Zou ,  Vito Dai

IPC: G03F7/20

CPC classification number: G03F7/70441 ,  B82Y30/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes, using a computing system, inputting a DSA target pattern. Using the computing system, a DSA model, an OPC model, and a MPC model, cooperatively running a DSA PC algorithm, an OPC algorithm, and a MPC algorithm to produce an output MPCed pattern for a mask writer to write on the photomask.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括产生用于在半导体衬底上形成DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括使用计算系统输入DSA目标图案。 使用计算系统，DSA模型，OPC模型和MPC模型，协作运行DSA PC算法，OPC算法和MPC算法，以产生用于掩模写入器在光掩模上写入的输出MPCed模式。

公开(公告)号：US08856698B1

公开(公告)日：2014-10-07

申请号：US13833104

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Azat Latypov

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265 ,  Y02T10/82

Abstract: A process and apparatus are provided for generating and evaluating one or more metrics for analyzing the design and manufacture of semiconductor devices. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Abstract translation: 提供了一种用于生成和评估用于分析半导体器件的设计和制造的一个或多个度量的过程和装置。 实施例包括扫描绘制的半导体设计布局以基于与预先表征的难以制造的图案的匹配来确定所绘制的半导体设计布局内的难以制造的图案，所述预先描述的难以制造的图案基于预定的相关性来确定校正的图案 校正图案和预先表征的难以制造图案，并且在所绘制的半导体设计布局内用修正图案代替难以制造的图案。

公开(公告)号：US08667428B1

公开(公告)日：2014-03-04

申请号：US13659453

申请日：2012-10-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov

IPC: G06F17/50 ,  G06F19/00 ,  G06K9/00 ,  G21K5/00 ,  G03F1/00 ,  G03F1/36 ,  G03F1/38

CPC classification number: G06F17/5081 ,  G03F1/0069 ,  G03F1/0092 ,  G03F1/36 ,  G03F1/38 ,  G03F7/0002 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G21K5/00

Abstract: In an exemplary embodiment, a method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. The step of designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern.

Abstract translation: 在示例性实施例中，制造集成电路的方法包括设计用于在半导体衬底上的光致抗蚀剂层中形成预图案开口的光学光掩模，其中光致抗蚀剂层和预图案开口被涂覆有自组装 经过定向自组装（DSA）形成DSA图案的材料。 设计光学光掩模的步骤包括使用计算系统，输入DSA目标图案，以及使用计算系统，将DSA模型应用于DSA目标图案以生成第一DSA定向图案。 此外，设计光学光掩模的步骤包括使用计算系统，计算DSA目标模式和DSA指导模式之间的残差，并使用计算系统，将DSA模型应用于第一DSA指导模式，并且剩余生成 第二个更新的DSA指导模式。

公开(公告)号：US20160247686A1

公开(公告)日：2016-08-25

申请号：US14630676

申请日：2015-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Azat Latypov ,  Tamer Coskun ,  Moshe Preil

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/0002 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括形成多个形貌特征的基本上周期性的阵列，包括多个耐蚀刻的地形特征和至少一个划线斑点特征。 多个耐蚀刻的形貌特征限定了多个耐蚀刻限制孔，并且所述至少一个划线阱特征限定了具有与耐蚀刻限制孔不同的尺寸和/或形状的划线阱限制阱。 将嵌段共聚物沉积到限制孔中。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 耐蚀刻的地形特征指示耐蚀刻相，在每个耐蚀刻限制孔中形成耐蚀刻塞。

公开(公告)号：US09208275B2

公开(公告)日：2015-12-08

申请号：US14189465

申请日：2014-02-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei-Long Wang ,  Azat Latypov ,  Yi Zou ,  Tamer Coskun

IPC: G06F17/50 ,  G03F1/00 ,  H01L21/027 ,  H01L21/311

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  H01L21/0271 ,  H01L21/0274 ,  H01L21/31133

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes inputting DSA target patterns. The DSA target patterns are grouped into groups including a first group and a group boundary is defined around the first group as an initial OPC mask pattern. A circle target is generated around each of the DSA target patterns in the first group to define a merged circle target boundary. The initial OPC mask pattern is adjusted and/or iteratively updated using the merged circle target boundary to generate an output final OPC mask pattern.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括生成用于形成覆盖半导体衬底的DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括输入DSA目标图案。 DSA目标图案被分组成包括第一组的组，并且组边界围绕第一组被定义为初始OPC掩模模式。 围绕第一组中的每个DSA目标图案生成圆目标以定义合并的圆目标边界。 使用合并的圆目标边界来调整和/或迭代地更新初始OPC掩模图案以生成输出的最终OPC掩模图案。

公开(公告)号：US20150339429A1

公开(公告)日：2015-11-26

申请号：US14285739

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yi Zou ,  Wei-Long Wang ,  Azat Latypov ,  Tamer Coskun

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G03F7/0002 ,  G06F17/5068 ,  H01L21/0271

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括生成用于形成覆盖半导体衬底的DSA定向图案的光掩模。 DSA引导图案被配置为引导沉积在其上的自组装材料经历定向自组装（DSA）以形成DSA图案。 生成光掩模包括在设计布局中标识DSA目标图案的位置。 DSA目标模式被分组成包括第一组的组，并且围绕第一组定义第一组边界。 所述方法还包括确定到所述第一组边界的相邻DSA目标图案是否是距离在所述第一组边界内的相邻DSA目标图案至少预定的最小保持距离。 该方法还包括确定第一组中的DSA目标模式是否兼容DSA。 使用第一组边界生成输出掩模图案。