公开(公告)号：US20190043956A1

公开(公告)日：2019-02-07

申请号：US16018304

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/16 ,  H01L21/02

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

公开(公告)号：US09972620B2

公开(公告)日：2018-05-15

申请号：US15234762

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charan V. Surisetty ,  Dominic J. Schepis ,  Kangguo Cheng ,  Alexander Reznicek

IPC: H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791

Abstract: Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.

公开(公告)号：US09754941B2

公开(公告)日：2017-09-05

申请号：US14729845

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/18 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L29/161

CPC classification number: H01L27/0924 ,  H01L21/18 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.

公开(公告)号：US20160358922A1

公开(公告)日：2016-12-08

申请号：US14729845

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/18 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.

Abstract translation: 提供一种形成半导体结构的方法，其包括具有第一锗含量的压缩应变硅锗合金翅片和具有小于第一锗含量的第二锗含量的拉伸应变硅锗合金翅片。 不同的应变和锗含量的硅锗合金翅片位于同一基板上。 该方法包括在一组硅锗合金翅片周围形成硅包覆层，并且在另一组硅锗合金翅片周围形成含锗材料包层。 然后使用热混合形成不同的应变和锗含量的硅锗合金翅片。

公开(公告)号：US20160343623A1

公开(公告)日：2016-11-24

申请号：US14718760

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract translation: 通过使用掺杂氧化物的体积FinFET结构形成穿通停止层。 通过退火将掺杂剂驱入散热片的基板和基部。 穿通停止层包括p型区域和n型区域，它们都可以延伸到半导体鳍片中基本相等的距离。

公开(公告)号：US09385023B1

公开(公告)日：2016-07-05

申请号：US14712462

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joel P. de Souza ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/76 ,  H01L27/12 ,  H01L21/70 ,  H01L21/762 ,  H01L21/225 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/76245 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height that is located on a first buried oxide structure. The structure further includes a second silicon fin of a second height that is located on a second buried oxide structure that is spaced apart from the first buried oxide structure. The second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar of a topmost surface with the second silicon fin.

Abstract translation: 提供了包含具有不同高度的硅散热片的半导体结构，同时为了工艺可行性而保持合理的翅片高宽比。 半导体结构包括位于第一掩埋氧化物结构上的第一高度的第一硅鳍。 该结构还包括第二高度的第二硅片，其位于与第一掩埋氧化物结构间隔开的第二掩埋氧化物结构上。 第二硅片的第二高度大于第一硅片的第一高度，但是第一硅片的最顶面与第二硅片的最顶面共面。

公开(公告)号：US20160190302A1

公开(公告)日：2016-06-30

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/167 ,  H01L21/84 ,  H01L21/02 ,  H01L21/322 ,  H01L21/324 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

Abstract translation: 一种制造半导体器件的方法，其中：（i）所述散热片形成在多孔半导体材料层（例如，硅层）上; 和（ii）然后氧化多孔半导体层以形成绝缘体层（例如，SiO 2掩埋氧化物层）。 多孔半导体层中的孔促进了绝缘体层的可靠氧化，允许气态氧（O 2）在整个层中被氧化以形成绝缘体层。 在这些实施例的一些中，薄的无孔半导体层位于多孔半导体层之上（在其氧化之前），以允许材料的应变外延生长用于制造成品半导体器件的源极区域和漏极区域（用于 例如，FINFET）。

公开(公告)号：US20160181095A1

公开(公告)日：2016-06-23

申请号：US14574533

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kanggou Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/02532 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02587 ,  H01L21/02612 ,  H01L21/02664 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/66795

Abstract: Embodiments of the invention include a method for fabricating a SiGe fin and the resulting structure. A SOI substrate is provided, including at least a silicon layer on top of a BOX. At least one fin upon a thin layer of silicon and a hard mask layer over the at least one fin is formed using the silicon layer on top of the BOX. A SiGe layer is epitaxially grown from exposed portions of the fin and the thin layer of silicon. Spacers are formed on sidewalls of the hard mask. Regions of the SiGe layer and the thin layer of silicon not protected by the spacers are etched, such that portions of the BOX are exposed. A condensation process converts the fin to SiGe and to convert the SiGe layer to oxide. The hard mask, the spacers, and the oxide layer are removed.

Abstract translation: 本发明的实施例包括制造SiGe鳍片的方法和所得到的结构。 提供SOI衬底，其至少包括在BOX顶部的硅层。 使用BOX顶部的硅层，在至少一个散热片上的薄层硅层和硬掩模层上形成至少一个鳍片。 SiGe层从翅片和薄层硅的暴露部分外延生长。 垫片形成在硬掩模的侧壁上。 SiGe层的区域和未被间隔物保护的硅的薄层被蚀刻，使得BOX的部分被暴露。 冷凝过程将翅片转换成SiGe并将SiGe层转化为氧化物。 去除硬掩模，间隔物和氧化物层。

公开(公告)号：US20160133727A1

公开(公告)日：2016-05-12

申请号：US14537832

申请日：2014-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure, such as a FinFET, etc., includes a bi-portioned junction. The bi-portioned junction includes a doped outer portion and a doped inner portion. The dopant concentration of the outer portion is less than the dopant concentration of the inner portion. An electrical connection is formed by diffusion of the dopants within outer portion into a channel region and diffusion of the dopants within the outer portion into the inner region. A low contact resistance is achieved by a contact electrically contacting the relatively higher doped inner portion while device shorting is limited by the relatively lower doped outer portion.

Abstract translation: 诸如FinFET等的半导体结构包括双分支结。 双分支结包括掺杂的外部部分和掺杂的内部部分。 外部部分的掺杂剂浓度小于内部部分的掺杂剂浓度。 通过将外部部分内的掺杂剂扩散到沟道区域中并且将外部部分内的掺杂剂扩散到内部区域中来形成电连接。 低接触电阻通过电接触相对较高的掺杂内部部分的接触来实现，同时器件短路由相对较低的掺杂外部部分限制。

公开(公告)号：US09634142B1

公开(公告)日：2017-04-25

申请号：US15076699

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pouya Hashemi ,  Kangguo Cheng

IPC: H01L21/324 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A method may include forming a germanium-including fin on a substrate, and forming a dummy gate extending over the germanium-including fin, creating a channel under the gate and a source/drain region of the germanium-including fin extending from under the dummy gate on each side of the dummy gate. An in-situ p-type doped silicon germanium layer may be grown over the source/drain region, the germanium-including fin having a higher concentration of germanium than the in-situ p-type doped silicon germanium layer. An anneal thermally mixes the germanium of the in-situ p-type doped silicon germanium layer and the germanium of the germanium-including fin in the source/drain region of the germanium-including fin and diffuses the p-type dopant of the in-situ p-type doped silicon germanium layer into the channel of the germanium-including fin, forming a source/drain extension. A portion of the channel has a higher germanium concentration than the source/drain region.