公开(公告)号：US09653573B2

公开(公告)日：2017-05-16

申请号：US14827510

申请日：2015-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US09728649B2

公开(公告)日：2017-08-08

申请号：US15009906

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/786 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

公开(公告)号：US09379135B2

公开(公告)日：2016-06-28

申请号：US14723681

申请日：2015-05-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/76205 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region.

公开(公告)号：US20160163879A1

公开(公告)日：2016-06-09

申请号：US15009906

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

Abstract translation: 公开了一种半导体器件。 半导体器件可以包括设置在衬底上的第一介电层; 设置在所述第一电介质层上的一组偏置线; 第二电介质层，设置在所述第一电介质层上和所述一组偏置线之间，其中所述第二电介质层的厚度小于所述第一介电层的厚度; 设置在所述第二电介质层的部分上的图案化半导体层; 以及设置在所述偏置线组之上的图案化半导体层上的一组器件。

公开(公告)号：US09281198B2

公开(公告)日：2016-03-08

申请号：US13900808

申请日：2013-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L21/28 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.

Abstract translation: 公开了一种形成半导体器件的方法。 该方法包括在基底上形成第一介电层; 在所述第一电介质层上形成一组偏置线; 用第二电介质层覆盖该组偏置线; 在所述第二电介质层上形成半导体层; 以及在所述偏置线组之上的半导体层上形成一组器件。

公开(公告)号：US09224607B2

公开(公告)日：2015-12-29

申请号：US14029896

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

IPC: H01L27/146 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/28 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/66628

Abstract: A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region.

Abstract translation: 半导体器件包括具有相反极性的第一器件区域和第二器件区域。 每个器件区域至少包括晶体管器件和相关联的外延。 形成高k屏障以仅覆盖第一器件区域外延。 高k屏障可以包括形成在第一器件区域外延的顶表面上的基本上水平的部分和形成在第一器件区域外延的外表面上的基本上垂直的部分。 基本上垂直的部分可以将第一器件区域与第二器件区域部分隔离。

公开(公告)号：US08809920B2

公开(公告)日：2014-08-19

申请号：US13670674

申请日：2012-11-07

Applicant: International Business Machines Corporation ,  GlobalFoundries Inc.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/76

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US09190487B2

公开(公告)日：2015-11-17

申请号：US14283409

申请日：2014-05-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US20140256106A1

公开(公告)日：2014-09-11

申请号：US14283409

申请日：2014-05-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

公开(公告)号：US20140124840A1

公开(公告)日：2014-05-08

申请号：US13670674

申请日：2012-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。