公开(公告)号：US11355599B2

公开(公告)日：2022-06-07

申请号：US16995397

申请日：2020-08-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Kiok Boone Quek

IPC: H01L29/792 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/20

Abstract: Methods of forming a ferroelectric material layer below a field plate for achieving increased Vbr with reduced Rdson and resulting devices are provided. Embodiments include forming a N-Drift in a portion of the Si layer formed in a portion of a p-sub; forming an oxide layer over portions of the Si layer and the N-Drift; forming a gate over a portion of the oxide layer; forming a S/D extension region in the Si layer; forming first and second spacers on opposite sides of the gate and the oxide layer; forming a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift remote from the Si layer; forming a U-shaped ferroelectric material layer over the oxide layer and the N-Drift, proximate or adjacent to the gate; and filling the U-shaped ferroelectric material layer with a metal, a field gate formed.

公开(公告)号：US10522614B2

公开(公告)日：2019-12-31

申请号：US15904004

申请日：2018-02-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yongtian Hou ,  Khee Yong Lim ,  Ming-Tsang Tsai ,  Elgin Kiok Boone Quek

IPC: H01L29/788 ,  H01L49/02 ,  H01L29/51 ,  H01L29/78 ,  H01L27/108 ,  H01L21/768 ,  H01L27/11507 ,  H01L29/423 ,  H01L21/28

Abstract: Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.

公开(公告)号：US10388852B2

公开(公告)日：2019-08-20

申请号：US15176172

申请日：2016-06-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Eng Huat Toh ,  Elgin Kiok Boone Quek

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Devices and methods for forming a device are disclosed. A substrate having circuit component formed on a substrate surface is provided. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A pair of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.

公开(公告)号：US20160111629A1

公开(公告)日：2016-04-21

申请号：US14518696

申请日：2014-10-20

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Xuan Anh Tran ,  Elgin Kiok Boone Quek

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer.

Abstract translation: 制造STT-MRAM集成电路的方法包括：在底部电极层上形成固定层，在固定的上形成氧化硅层，硬掩模层，并在氧化硅和硬掩模层内形成沟槽，从而暴露出上表面 的氧化硅和硬掩模层的固定层和侧壁。 该方法还包括沿着氧化硅和硬掩模层的侧壁并且在固定层的上表面上方形成共形阻挡层，使得保形阻挡层包括邻近氧化硅和硬掩模层的侧壁的侧壁部分和 侧壁部分之间的中心部分并且与固定层的上表面相邻。 该方法还包括在阻挡层的侧壁部分和阻挡层的中心部分之间形成自由层。

公开(公告)号：US10720513B2

公开(公告)日：2020-07-21

申请号：US15917147

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Kiok Boone Quek

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/112 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L27/115 ,  H01L21/84

Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.

公开(公告)号：US20190280108A1

公开(公告)日：2019-09-12

申请号：US15917147

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Kiok Boone Quek

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/112 ,  H01L27/115 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06

Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.

公开(公告)号：US20190237658A1

公开(公告)日：2019-08-01

申请号：US15882362

申请日：2018-01-29

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Yinjie Ding ,  Kangho Lee ,  Elgin Kiok Boone Quek

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L29/78

Abstract: Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.

公开(公告)号：US10121959B1

公开(公告)日：2018-11-06

申请号：US15625272

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yinjie Ding ,  Eng Huat Toh ,  Kangho Lee ,  Elgin Kiok Boone Quek

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a segmented FDSOI STT-MRAM using dummy WL blocks and the resulting device are provided. Embodiments include forming a plurality of FDSOI STT-MRAM active WL blocks laterally separated across a memory array; forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block; forming a plurality of SL structures laterally separated across the memory array; forming a plurality of BL structures laterally separated across the memory array; and connecting the plurality of SL and BL structures to the plurality of active WL blocks.

公开(公告)号：US09362374B2

公开(公告)日：2016-06-07

申请号：US14253878

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng Tan ,  Eng Huat Toh ,  Jeoung Mo Koo ,  Danny Shum ,  Elgin Kiok Boone Quek

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/115 ,  G11C16/04

CPC classification number: H01L29/42324 ,  G11C16/0425 ,  H01L27/11558 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. A non-volatile MTP memory cell includes a substrate, first and second wells disposed in the substrate, a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well and sharing a diffusion region. The memory cell further includes a control gate disposed over the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and the second wells.

Abstract translation: 提出了一种用于非易失性存储单元的简单且无成本的多时间可编程（MTP）结构的实施例。 非易失性MTP存储单元包括衬底，设置在衬底中的第一和第二阱，具有选择栅极的第一晶体管和具有彼此相邻并且布置在第二阱上并且共享扩散区域的浮置栅极的第二晶体管。 存储单元还包括设置在第一阱上的控制栅极。 控制栅极耦合到浮动栅极，并且控制和浮置栅极包括延伸穿过第一和第二阱的相同栅极层。

公开(公告)号：US09312268B2

公开(公告)日：2016-04-12

申请号：US14474578

申请日：2014-09-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Shyue Seng Jason Tan ,  Elgin Kiok Boone Quek ,  Danny Shum

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/33 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11524 ,  H01L27/11546 ,  H01L27/11548 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括：形成覆盖基板的第一和第二鳍片，其中第一鳍片和第二鳍片在鳍片交叉点相交。 第一鳍有第一鳍左端。 隧道电介质和浮动栅极与浮动栅极和第一鳍片之间的隧道电介质相邻地形成在第一鳍片附近。 在浮置栅极附近形成互补电介质，并且在多晶硅电介质附近形成控制栅极，使得多晶硅电介质位于浮置栅极和控制栅极之间。 除了在第一翅片左端和鳍片交叉点之间的浮动位置处，控制栅极，互间电介质，浮动栅极和隧道电介质从第一鳍片上除去。