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公开(公告)号：US11355599B2
公开(公告)日：2022-06-07
申请号：US16995397
申请日：2020-08-17
IPC分类号： H01L29/792 , H01L29/40 , H01L29/06 , H01L29/10 , H01L29/78 , H01L29/66 , H01L29/51 , H01L21/28 , H01L29/20
摘要： Methods of forming a ferroelectric material layer below a field plate for achieving increased Vbr with reduced Rdson and resulting devices are provided. Embodiments include forming a N-Drift in a portion of the Si layer formed in a portion of a p-sub; forming an oxide layer over portions of the Si layer and the N-Drift; forming a gate over a portion of the oxide layer; forming a S/D extension region in the Si layer; forming first and second spacers on opposite sides of the gate and the oxide layer; forming a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift remote from the Si layer; forming a U-shaped ferroelectric material layer over the oxide layer and the N-Drift, proximate or adjacent to the gate; and filling the U-shaped ferroelectric material layer with a metal, a field gate formed.
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公开(公告)号：US10522614B2
公开(公告)日：2019-12-31
申请号：US15904004
申请日：2018-02-23
IPC分类号： H01L29/788 , H01L49/02 , H01L29/51 , H01L29/78 , H01L27/108 , H01L21/768 , H01L27/11507 , H01L29/423 , H01L21/28
摘要： Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.
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公开(公告)号：US10388852B2
公开(公告)日：2019-08-20
申请号：US15176172
申请日：2016-06-08
发明人： Ping Zheng , Eng Huat Toh , Elgin Kiok Boone Quek
摘要： Devices and methods for forming a device are disclosed. A substrate having circuit component formed on a substrate surface is provided. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A pair of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.
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4.发明申请INTEGRATED CIRCUIT STRUCTURES WITH SPIN TORQUE TRANSFER MAGNETIC RANDOM ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME 有权具有旋转转矩磁性随机存取存储器的集成电路结构及其制造方法公开(公告)号：US20160111629A1
公开(公告)日：2016-04-21
申请号：US14518696
申请日：2014-10-20
摘要： A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer.
摘要翻译： 制造STT-MRAM集成电路的方法包括：在底部电极层上形成固定层，在固定的上形成氧化硅层，硬掩模层，并在氧化硅和硬掩模层内形成沟槽，从而暴露出上表面 的氧化硅和硬掩模层的固定层和侧壁。 该方法还包括沿着氧化硅和硬掩模层的侧壁并且在固定层的上表面上方形成共形阻挡层，使得保形阻挡层包括邻近氧化硅和硬掩模层的侧壁的侧壁部分和 侧壁部分之间的中心部分并且与固定层的上表面相邻。 该方法还包括在阻挡层的侧壁部分和阻挡层的中心部分之间形成自由层。
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公开(公告)号：US10804323B2
公开(公告)日：2020-10-13
申请号：US16223074
申请日：2018-12-17
发明人： Xuan Anh Tran , Eng Huat Toh , Shyue Seng Tan , Yuan Sun , Elgin Kiok Boone Quek
摘要： Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.
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公开(公告)号：US10424568B1
公开(公告)日：2019-09-24
申请号：US16012415
申请日：2018-06-19
IPC分类号： H01L25/16 , H01L27/146 , H01L31/107 , H01L31/02
摘要： A method of forming a device including a SPAD detector and a BSI visible light sensor positioned on different planes, the device exhibiting improved resolution and pixel density are provided. Embodiments include a photodiode for detecting visible light; and a SPAD detector for detecting IR radiation, wherein the photodiode and the SPAD detector are on different planes.
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公开(公告)号：US10186554B2
公开(公告)日：2019-01-22
申请号：US15182625
申请日：2016-06-15
发明人： Eng Huat Toh , Yuan Sun , Elgin Kiok Boone Quek , Shyue Seng Tan , Xuan Anh Tran
摘要： Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure. The selector element includes respective first and second selector diodes for the first and second memory elements of each of the one or more cell stacks.
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公开(公告)号：US10163979B2
公开(公告)日：2018-12-25
申请号：US14483160
申请日：2014-09-11
发明人： Xuan Anh Tran , Eng Huat Toh , Shyue Seng Tan , Yuan Sun , Elgin Kiok Boone Quek
摘要： Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.
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公开(公告)号：US09583168B1
公开(公告)日：2017-02-28
申请号：US14985244
申请日：2015-12-30
IPC分类号： G11C11/00 , G11C11/16 , H01L27/22 , H01L43/02 , H01L43/08 , H01L23/528 , H01L29/06 , H01L29/10
CPC分类号： H01L29/1087 , G11C11/1659 , G11C11/1675 , H01L23/528 , H01L27/228 , H01L28/00 , H01L29/0649 , H01L43/02 , H01L43/08
摘要： A magnetic random access memory (MRAM) structure includes a source line connected to a source area of a semiconductor substrate, a magnetic tunnel junction (MTJ) connected to a drain area of the semiconductor substrate, and a gate disposed over the semiconductor substrate between the source area and the drain area. The MRAM structure further includes a contact structure that is configured to apply a first voltage bias to the gate and a means for applying a second voltage bias to the semiconductor substrate outside of the source area and the drain area.
摘要翻译： 磁性随机存取存储器（MRAM）结构包括连接到半导体衬底的源极区域的源极线，连接到半导体衬底的漏极区域的磁性隧道结（MTJ）以及设置在半导体衬底之间的栅极 源区和排水区。 MRAM结构还包括被配置为向栅极施加第一电压偏压的接触结构和用于将第二电压偏压施加到源极区域和漏极区域外的半导体衬底的装置。
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公开(公告)号：US09397146B2
公开(公告)日：2016-07-19
申请号：US14277808
申请日：2014-05-15
发明人： Eng Huat Toh , Yuan Sun , Elgin Kiok Boone Quek , Shyue Seng Tan , Xuan Anh Tran
CPC分类号： H01L27/249 , H01L27/0688 , H01L27/2409 , H01L27/2445 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure. The selector element includes respective first and second selector diodes for the first and second memory elements of each of the one or more cell stacks.
摘要翻译： 介绍了用于制造设备的设备和方法。 该器件包括衬底和设置在衬底上的垂直结构。 垂直结构包括一个或多个存储单元堆叠，每个两个相邻单元堆叠之间具有介电层。 一个或多个单元堆叠中的每一个分别包括在单元堆叠的第一和第二侧上的第一和第二第一类型导体; 第一和第二电极，与第一第一类型导体相邻的第一电极，与第二第一类型导体相邻的第二电极; 以及第一和第二存储元件，第一存储元件设置在第一第一型导体与第一电极之间，第二存储元件设置在第二第一型导体与第二电极之间。 该装置还包括选择器元件，其设置在基板上并且垂直地穿过垂直结构的中间部分。 选择器元件包括用于一个或多个单元堆叠中的每一个的第一和第二存储元件的相应的第一和第二选择二极管。
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