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    Thin film based passive devices and methods of forming the same
    1.
    发明授权
    Thin film based passive devices and methods of forming the same 有权

    公开(公告)号：US11942415B2

    公开(公告)日：2024-03-26

    申请号：US17888532

    申请日：2022-08-16

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Handoko Linewih ,  Chor Shu Cheng ,  Tze Ho Simon Chan ,  Yudi Setiawan

    IPC: H01L23/522 ,  H01L21/70 ,  H01L49/02

    CPC classification number: H01L23/5223 ,  H01L21/707 ,  H01L23/5226 ,  H01L23/5228 ,  H01L28/24 ,  H01L28/40

    Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

    Integrated circuit electrostatic discharge protection
    2.
    发明授权
    Integrated circuit electrostatic discharge protection 有权

    公开(公告)号：US10298215B2

    公开(公告)日：2019-05-21

    申请号：US15132563

    申请日：2016-04-19

    Applicant: Globalfoundries Singapore Pte. Ltd.

    Inventor： Wei Gao ,  Yi Lu ,  Handoko Linewih

    IPC: H02H9/04 ,  H03K5/08 ,  H01L27/02

    Abstract: Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.

    E-FUSE CELLS AND METHODS FOR PROTECTING E-FUSES
    3.
    发明申请
    E-FUSE CELLS AND METHODS FOR PROTECTING E-FUSES 审中-公开

    公开(公告)号：US20180350796A1

    公开(公告)日：2018-12-06

    申请号：US15609566

    申请日：2017-05-31

    Applicant: Globalfoundries Singapore Pte. Ltd.

    Inventor： Handoko Linewih ,  Chien-Hsin Lee

    IPC: H01L27/02 ,  H01L23/525 ,  H01L27/06

    Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.

    ONE-TIME PROGRAMMABLE FUSE USING THIN FILM RESISTOR LAYER, AND RELATED METHOD
    4.
    发明公开
    ONE-TIME PROGRAMMABLE FUSE USING THIN FILM RESISTOR LAYER, AND RELATED METHOD 审中-公开

    公开(公告)号：US20240212770A1

    公开(公告)日：2024-06-27

    申请号：US18145341

    申请日：2022-12-22

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Siow Lee Chwa ,  Handoko Linewih ,  Yudi Setiawan ,  Qiying Wong

    IPC: G11C17/16 ,  G11C17/18 ,  H01C7/00 ,  H01L23/525

    CPC classification number: G11C17/16 ,  G11C17/18 ,  H01C7/006 ,  H01L23/5256

    Abstract: A one-time programmable (OTP) fuse includes a fuse link including a thin film resistor (TFR) layer between a first insulator layer and a second insulator layer. A first terminal of the OTP fuse includes a first conductive pillar through one of the first and second insulator layers and in contact with the TFR layer; and a second terminal of the OTP fuse includes a second conductive pillar through one of the first and second insulator layers and in contact with the TFR layer. The second conductive pillar and the TFR layer have a lateral contact interface having a same shape as an outer portion of the second conductive pillar. The second conductive pillar does not simply land on the TFR layer, but extends through it. Application of a current to the OTP fuse results in programming via rupture of the lateral contact interface (not electromigration in the fuse link).

    LATERALLY-DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICES WITH A FIELD PLATE
    6.
    发明公开
    LATERALLY-DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICES WITH A FIELD PLATE 审中-公开

    公开(公告)号：US20240006529A1

    公开(公告)日：2024-01-04

    申请号：US17852514

    申请日：2022-06-29

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Surya Kris Amethystna ,  Guowei Zhang ,  Handoko Linewih ,  Jerry Joseph James

    IPC: H01L29/78 ,  H01L29/40 ,  H01L21/761

    CPC classification number: H01L29/7816 ,  H01L29/402 ,  H01L29/7835 ,  H01L21/761

    Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure comprises a semiconductor substrate including a first well, a second well positioned within the first well, a source region positioned in the first well, and a drain region positioned in the second well. The first well has a first conductivity type, and the second well, the source region, and the drain region have a second conductivity type opposite to the first conductivity type. The structure further comprises a field plate over the semiconductor substrate and a contact connecting the field plate to the drain region. The field plate is positioned to overlap with the drain region and with a portion of the second well adjacent to the drain region. The contact and the field plate comprise the same metal.

    Integrated thin film resistor and metal-insulator-metal capacitor
    7.
    发明授权
    Integrated thin film resistor and metal-insulator-metal capacitor 有权

    公开(公告)号：US11545486B2

    公开(公告)日：2023-01-03

    申请号：US17062292

    申请日：2020-10-02

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Chengang Feng ,  Yanxia Shao ,  Yudi Setiawan ,  Handoko Linewih ,  Xuesong Rao

    IPC: H01L27/06 ,  H01L49/02

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.

    ESD PROTECTION CIRCUIT
    8.
    发明申请
    ESD PROTECTION CIRCUIT 有权
    ESD保护电路

    公开(公告)号：US20130207179A1

    公开(公告)日：2013-08-15

    申请号：US13803091

    申请日：2013-03-14

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Da-Wei LAI ,  Handoko Linewih ,  Ying-Chang Lin

    IPC: H01L27/02

    CPC classification number: H01L27/0266 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7835

    Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.

    Abstract translation: 公开了一种装置，其包括用至少具有第一和第二晶体管的ESD保护电路的器件区限定的衬底。 每个晶体管包括具有第一和第二侧的栅极，与栅极的第一侧相邻的器件区域中的第一扩散区域，远离栅极的第二侧移位的器件区域中的第二扩散区域，以及 漂移隔离区域设置在栅极和第二扩散区域之间。 第一装置阱包围装置区域，第二装置井设置在第一装置井内。 该装置还包括包围第二扩散区域的漂移阱。 漂移井的边缘不延伸到门下方并远离通道区域。 排水井设置在第二扩散区域下方和漂移井内。

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