-
公开(公告)号：US20200098769A1
公开(公告)日：2020-03-26
申请号：US16695445
申请日：2019-11-26
IPC分类号： H01L27/11521 , H01L29/423 , H01L27/1159 , H01L27/11558 , H01L29/788 , H01L49/02 , H01L27/11524 , H01L29/49 , H01L29/51 , H01L29/10 , H01L29/66 , H01L29/78 , H01L29/08 , H01L21/28
摘要： Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively.
-
公开(公告)号：US20180269209A1
公开(公告)日：2018-09-20
申请号：US15459190
申请日：2017-03-15
IPC分类号： H01L27/105 , H01L29/423 , H01L29/788 , H01L27/12 , H01L27/06 , H01L29/78 , H01L29/66 , H01L21/84
摘要： Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.
-
公开(公告)号：US20170288131A1
公开(公告)日：2017-10-05
申请号：US15470936
申请日：2017-03-28
CPC分类号： H01L43/065 , G01R33/0052 , G01R33/07 , H01L43/04 , H01L43/14
摘要： An integrated Hall effect sensor is disclosed. The integrated Hall effect sensor has high tunable sensitivity by varying the thickness of the Hall plate. The Hall effect sensor is integrated onto a crystalline-on-insulator substrate, such as silicon-on-insulator (SOI) substrate. The Hall plate is part of the surface substrate of the SOI substrate. A sensor well is disposed in the bulk substrate of the SOI substrate. By applying an appropriate well bias voltage, the thickness of the Hall plate can be tuned from below the surface substrate to achieve the desired sensitivity. A gate may also be provided on the surface substrate. Biasing the gate with an appropriate gate bias voltage can further enhance thickness tunability of the Hall plate from above to achieve the desired sensitivity.
-
公开(公告)号：US20160225429A1
公开(公告)日：2016-08-04
申请号：US15012736
申请日：2016-02-01
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1657 , G11C11/1659 , G11C11/1673 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12
摘要： Memory cells and methods for forming a memory cell are presented. The memory cell includes a storage unit and a selector unit. The storage unit includes a magnetic storage element with first and second storage terminals and a bitline coupled to the second storage terminal. The selector unit includes a first selector and a second selector. The first selector may be a tunneling select transistor or a metal oxide semiconductor select transistor. The second tunneling select transistor is configured to have a second unidirectional current flow between its source and drain terminals. The second selector serves at least as a read selector for read operations of the memory cell and a read current is in the direction of the second unidirectional current flow between the source drain terminals of the second selector.
摘要翻译： 介绍了存储单元和形成存储单元的方法。 存储单元包括存储单元和选择器单元。 存储单元包括具有第一和第二存储终端的磁存储元件和耦合到第二存储终端的位线。 选择器单元包括第一选择器和第二选择器。 第一选择器可以是隧穿选择晶体管或金属氧化物半导体选择晶体管。 第二隧道选择晶体管被配置为在其源极和漏极端子之间具有第二单向电流。 第二选择器至少用作存储单元的读取操作的读取选择器，并且读取电流在第二选择器的源极漏极之间的第二单向电流流动的方向上。
-
公开(公告)号：US20240347664A1
公开(公告)日：2024-10-17
申请号：US18300110
申请日：2023-04-13
IPC分类号： H01L31/107 , H01L27/144 , H01L31/02 , H01L31/0352
CPC分类号： H01L31/107 , H01L27/1446 , H01L31/02027 , H01L31/0352
摘要： The present disclosure relates to semiconductor structures and, more particularly, to single-photon avalanche diodes and methods of manufacture. The structure includes: a first deep trench structure in a semiconductor substrate having a conductive material and a material of a first polarity; a second deep trench structure in the semiconductor substrate surrounding the first deep trench structure, the second deep trench structure having a conductive material and a material of a second polarity; and contacts to both the first deep trench structure and the second deep trench structure.
-
公开(公告)号：US20190393338A1
公开(公告)日：2019-12-26
申请号：US16013336
申请日：2018-06-20
摘要： The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.
-
公开(公告)号：US20170186852A1
公开(公告)日：2017-06-29
申请号：US14981980
申请日：2015-12-29
IPC分类号： H01L29/66 , H01L21/266 , H01L21/265 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66575 , H01L21/26506 , H01L21/26513 , H01L29/105 , H01L29/167 , H01L29/6659
摘要： A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.
-
公开(公告)号：US20160233333A1
公开(公告)日：2016-08-11
申请号：US15040981
申请日：2016-02-10
CPC分类号： H01L43/12 , H01L27/228 , H01L29/0669 , H01L29/165 , H01L29/7834 , H01L29/7848
摘要： Memory cells and methods of forming memory cells are disclosed. The memory cell includes a substrate and a select transistor. The select transistor includes a gate disposed over the substrate between first and second source/drain (S/D) terminals. The first and second S/D terminals are configured such that a resistance at the second S/D terminal is higher than a resistance at the first S/D terminal. A dielectric layer disposed over the substrate includes a plurality of inter level dielectric (ILD) layers. A lower portion of the dielectric layer includes a first contact level and a first metal level. A first contact plug disposed within the first contact level connects the first S/D terminal to a first metal line in the first metal level. A magnetic tunnel junction (MTJ) element is disposed directly on and in contact with a top of the first metal line.
摘要翻译： 公开了存储单元和形成存储单元的方法。 存储单元包括衬底和选择晶体管。 选择晶体管包括设置在第一和第二源极/漏极（S / D）端子之间的衬底上的栅极。 第一和第二S / D端子被配置为使得第二S / D端子处的电阻高于第一S / D端子处的电阻。 布置在衬底上的电介质层包括多个级间电介质层（ILD）层。 电介质层的下部包括第一接触电平和第一金属电平。 设置在第一接触电平内的第一接触插头将第一S / D端子连接到第一金属层中的第一金属线。 磁性隧道结（MTJ）元件直接设置在第一金属线的顶部并与之接触。
-
公开(公告)号：US20240194714A1
公开(公告)日：2024-06-13
申请号：US18064890
申请日：2022-12-12
发明人： Ping ZHENG , Eng Huat TOH , Cancan WU , Kiok Boone Elgin QUEK
IPC分类号： H01L27/146
CPC分类号： H01L27/1463 , H01L27/1462 , H01L27/14627 , H01L27/14683
摘要： A photodiode device includes a semiconductor substrate, a plurality of pixels, each of the pixels including a diode structure on a first side of the substrate and a conductive layer on a second side of the substrate, and DTI structures isolating adjacent pixels from one another, the DTI structures including a conductive material that electrically couples the conductive layer on the second side of the substrate and a metal line on the first side of the substrate. The conductive material in the DTI structures is part of an electrode circuit for the pixels.
-
公开(公告)号：US20220205948A1
公开(公告)日：2022-06-30
申请号：US17699219
申请日：2022-03-21
发明人： Lanxiang WANG , Bin LIU , Eng Huat TOH , Shyue Seng TAN , Kiok Boone Elgin QUEK
IPC分类号： G01N27/414 , H01L29/16 , H01L29/04
摘要： According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.
-
-
-
-
-
-
-
-
-
搜索结果
35 条记录 (耗时 0.018 秒)
