HOME AGENT DATA AND MEMORY MANAGEMENT
    1.
    发明申请
    HOME AGENT DATA AND MEMORY MANAGEMENT 失效
    家庭代理数据和内存管理

    公开(公告)号:US20110078492A1

    公开(公告)日:2011-03-31

    申请号:US12571381

    申请日:2009-09-30

    IPC分类号: G06F11/00 G06F12/08 G06F12/00

    CPC分类号: G06F12/0817

    摘要: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.

    摘要翻译: 描述与归属代理数据和存储器管理有关的方法和装置。 在一个实施例中,洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。 在一个实施例中,映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。 还公开了其他实施例。

    Home agent data and memory management
    4.
    发明授权
    Home agent data and memory management 失效
    家庭代理数据和内存管理

    公开(公告)号:US08327228B2

    公开(公告)日:2012-12-04

    申请号:US12571381

    申请日:2009-09-30

    IPC分类号: G11C29/00

    CPC分类号: G06F12/0817

    摘要: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.

    摘要翻译: 描述与归属代理数据和存储器管理有关的方法和装置。 在一个实施例中,洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。 在一个实施例中,映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。 还公开了其他实施例。

    Bus interface adapted to coalesce snoop responses
    7.
    发明授权
    Bus interface adapted to coalesce snoop responses 有权
    总线接口适用于聚合侦听响应

    公开(公告)号:US07783843B2

    公开(公告)日:2010-08-24

    申请号:US11130536

    申请日:2005-05-16

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    CPC分类号: G06F12/0831

    摘要: In a bus interface adapted for usage in a multiple-core processor, an interface couples a bus to the one or more processor cores. The bus interface comprises a queue coupled to the interface which is adapted to receive snoop responses from the processor cores and coalesce snoop responses from the processor cores into a single snoop response that reflects snoop responses from all processor cores.

    摘要翻译: 在适于在多核处理器中使用的总线接口中,接口将总线耦合到一个或多个处理器核心。 总线接口包括耦合到接口的队列,其适于从处理器核接收窥探响应并将来自处理器核心的窥探响应聚合成反映来自所有处理器核心的窥探响应的单个侦听响应。