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公开(公告)号：US20120313647A1
公开(公告)日：2012-12-13
申请号：US13156836
申请日：2011-06-09
IPC分类号： G01R27/28
CPC分类号： G11C29/025 , G01R31/2882 , G11C7/10 , G11C29/50012 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的基础设施的方法和系统。 关键路径监控电路（基础设施）被配置为从第一层中的发射点发射信号，第一层是第一电路。 基础设施还被配置为创建到捕获点的电路径。 信号从第一层的发射点发射。 测量电路径的性能特征，从而进行测量，其中测量表示当与3D堆叠中的第二层堆叠时的第一层的性能，而不会在3D堆叠中实际堆叠第一层和第二层 ，第二层是第二电路。
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2.发明授权Bonding controller guided assessment and optimization for chip-to-chip stacking 有权键合控制器引导评估和优化，用于芯片到芯片堆叠公开(公告)号：US08543959B2
公开(公告)日：2013-09-24
申请号：US13087464
申请日：2011-04-15
IPC分类号： G06F17/50
CPC分类号： H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.
摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的方法，系统和计算机程序产品。 从用于堆叠的候选芯片的集合中选择第一候选芯片，所述候选芯片组中的每个候选芯片包括集成电路。 在第一候选芯片中激活3D性能决定因素的一部分。 对于一组操作条件测量性能参数的值。 使用该值计算第一候选芯片的堆叠性能值。 所述候选芯片组的子集被堆叠在堆叠中，所述子集包括第一候选芯片，使得当以第一顺序堆叠时子集的性能参数的组合值在所述性能的值的确定范围内 参数。
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公开(公告)号：US09251913B2
公开(公告)日：2016-02-02
申请号：US13156836
申请日：2011-06-09
CPC分类号： G11C29/025 , G01R31/2882 , G11C7/10 , G11C29/50012 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的基础设施的方法和系统。 关键路径监控电路（基础设施）被配置为从第一层中的发射点发射信号，第一层是第一电路。 基础设施还被配置为创建到捕获点的电路径。 信号从第一层的发射点发射。 测量电路径的性能特征，从而进行测量，其中测量表示当与3D堆叠中的第二层堆叠时的第一层的性能，而不会在3D堆叠中实际堆叠第一层和第二层 ，第二层是第二电路。
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4.发明申请BONDING CONTROLLER GUIDED ASSESSMENT AND OPTIMIZATIONFOR CHIP-TO-CHIP STACKING 有权绑定控制器指导评估和优化芯片到芯片堆栈公开(公告)号：US20120266125A1
公开(公告)日：2012-10-18
申请号：US13087464
申请日：2011-04-15
IPC分类号： G06F17/50
CPC分类号： H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.
摘要翻译： 在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的方法，系统和计算机程序产品。 从用于堆叠的候选芯片的集合中选择第一候选芯片，所述候选芯片组中的每个候选芯片包括集成电路。 在第一候选芯片中激活3D性能决定因素的一部分。 对于一组操作条件测量性能参数的值。 使用该值计算第一候选芯片的堆叠性能值。 所述候选芯片组的子集被堆叠在堆叠中，所述子集包括第一候选芯片，使得当以第一顺序堆叠时子集的性能参数的组合值在所述性能的值的确定范围内 参数。
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公开(公告)号：US06650163B1
公开(公告)日：2003-11-18
申请号：US10216618
申请日：2002-08-08
IPC分类号： H03K300
CPC分类号： H03B5/1212 , H03B5/1228 , H03K3/354
摘要： A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.
摘要翻译： 一种包括时钟发生器的系统和集成电路（芯片），其包括片上电感器并且使用负载的固有电容来产生正弦时钟信号。 电感连接在电流源和反相开关之间。 开关的输出是基本上正弦信号，其直接连接到时钟驱动电路的至少一部分而没有中间缓冲。 在优选实施例中，时钟发生器是双相设计，其包括一对交叉耦合MOSFET，一对固态片上电感器和电流源。 每个片上电感器连接在MOSFET之一的电流源和漏极之间。 时钟发生器的输出被直接提供给芯片上至少一部分时钟驱动电路的时钟输入。 在该实施例中，时钟发生器输出信号的频率主要由电感元件的电感和时钟驱动电路的电容决定。 该设计消除了在时钟发生器本身中并入不同的电容器元件并产生时钟发生器的需要，其中大部分功率在发电机的感应元件和负载的电容元件之间振荡，从而减少由 当前来源。
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