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    Bandgap engineered MOS-gated power transistors
    3.
    发明申请
    Bandgap engineered MOS-gated power transistors 有权
    带隙工程MOS门控功率晶体管

    公开(公告)号：US20060118863A1

    公开(公告)日：2006-06-08

    申请号：US11245995

    申请日：2005-10-07

    申请人： Gary Dolny ,  Qi Wang ,  Ihsiu Ho

    发明人： Gary Dolny ,  Qi Wang ,  Ihsiu Ho

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7782 ,  Y02P70/605

    摘要： Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A body tie on this device can also be eliminated to reduce transistor cell size. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Device characteristics are also improved. For example, parasitic gate impedance is reduced through the use of a poly SiGe gate, and channel resistance is reduced through the use of a SiGe layer near the device's gate.

    摘要翻译： 提高对瞬态电压的抗扰度并减少寄生阻抗的器件，方法和过程。 提高对松开感应开关事件的抗扰度。 例如，提供了具有SiGe源的沟槽门控功率MOSFET器件，其中SiGe源通过减少主体或阱区中的空穴电流来降低寄生npn晶体管增益，从而降低闩锁状态的可能性。 也可以消除该器件上的身体接合以减少晶体管电池尺寸。 还提供了具有SiGe体或阱区的沟槽栅功率MOSFET器件。 当体二极管导通时，SiGe体减小空穴电流，从而降低反向恢复功率损耗。 设备特性也得到改善。 例如，通过使用多晶硅栅极减少寄生栅极阻抗，并且通过在器件栅极附近使用SiGe层来减小沟道电阻。

    Bandgap engineered MOS-gated power transistors
    4.
    发明授权
    Bandgap engineered MOS-gated power transistors 有权
    带隙工程MOS门控功率晶体管

    公开(公告)号：US07755137B2

    公开(公告)日：2010-07-13

    申请号：US11245995

    申请日：2005-10-07

    申请人： Gary Dolny ,  Qi Wang

    发明人： Gary Dolny ,  Qi Wang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7782 ,  Y02P70/605

    摘要： Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A body tie on this device can also be eliminated to reduce transistor cell size. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Device characteristics are also improved. For example, parasitic gate impedance is reduced through the use of a poly SiGe gate, and channel resistance is reduced through the use of a SiGe layer near the device's gate.

    摘要翻译： 提高对瞬态电压的抗扰度并减少寄生阻抗的器件，方法和过程。 提高对松开感应开关事件的抗扰度。 例如，提供了具有SiGe源的沟槽门控功率MOSFET器件，其中SiGe源通过减少主体或阱区中的空穴电流来降低寄生npn晶体管增益，从而降低闩锁状态的可能性。 也可以消除该器件上的身体接合以减少晶体管电池尺寸。 还提供了具有SiGe体或阱区的沟槽栅功率MOSFET器件。 当体二极管导通时，SiGe体减小空穴电流，从而降低反向恢复功率损耗。 设备特性也得到改善。 例如，通过使用多晶硅栅极减少寄生栅极阻抗，并且通过在器件栅极附近使用SiGe层来减小沟道电阻。

    Trench-shielded semiconductor device
    6.
    发明授权
    Trench-shielded semiconductor device 有权
    沟槽屏蔽半导体器件

    公开(公告)号：US08148749B2

    公开(公告)日：2012-04-03

    申请号：US12389335

    申请日：2009-02-19

    申请人： Thomas E. Grebs ,  Mark Rinehimer ,  Joseph Yedinak ,  Dean E. Probst ,  Gary Dolny ,  John Benjamin

    发明人： Thomas E. Grebs ,  Mark Rinehimer ,  Joseph Yedinak ,  Dean E. Probst ,  Gary Dolny ,  John Benjamin

    IPC分类号： H01L29/02 ,  H01L21/332

    CPC分类号： H01L29/872 ,  H01L23/544 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/7811 ,  H01L29/8725 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

    摘要翻译： 描述了用于改善沟槽屏蔽功率半导体器件等的性能的各种结构和方法。 示例性器件包括具有表面的半导体区域，半导体区域的第一区域，设置在半导体区域中并围绕第一区域的第一导电类型的阱区域以及在半导体区域中延伸的多个沟槽。 每个沟槽具有设置在阱区的第一部分中的第一端，设置在阱区的第二部分中的第二端和在第一和第二端之间的中间部分，并且设置在第一区域中。 每个沟槽还具有排列有电介质层的相对侧壁，以及设置在电介质层的至少一部分上的导电电极。

    Semiconductor devices and methods for making the same
    7.
    发明授权
    Semiconductor devices and methods for making the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08129778B2

    公开(公告)日：2012-03-06

    申请号：US12629232

    申请日：2009-12-02

    申请人： Suku Kim ,  James J. Murphy ,  Gary Dolny

    发明人： Suku Kim ,  James J. Murphy ,  Gary Dolny

    IPC分类号： H01L21/00

    CPC分类号： H01L29/8083 ,  H01L29/0634 ,  H01L29/1066 ,  H01L29/7722

    摘要： Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.

    摘要翻译： 描述了用于制造这种特别适用于高频应用的器件的半导体器件和方法。 半导体器件将SIT（或结型场效应晶体管[JFET]）结构与PN超结结构相结合。 SIT结构可以使用包含夹在厚介电层之间的栅极的沟槽形成。 当栅极垂直夹在沟槽中的两个隔离区域之间时，其也连接到一个导电类型的超结结构的区域，从而允许控制半导体器件的电流路径。 这种半导体器件相对于传统的平面栅极和凹入栅极SIT半导体器件具有较低的电阻率和电容。 描述其他实施例。

    PN junction and MOS capacitor hybrid resurf transistor
    8.
    发明授权
    PN junction and MOS capacitor hybrid resurf transistor 有权
    PN结和MOS电容混合复用晶体管

    公开(公告)号：US08076722B2

    公开(公告)日：2011-12-13

    申请号：US12845919

    申请日：2010-07-29

    申请人： Steven Leibiger ,  Gary Dolny

    发明人： Steven Leibiger ,  Gary Dolny

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7835 ,  H01L27/088 ,  H01L27/0927 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/66659

    摘要： A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack.

    摘要翻译： 诸如RESURF晶体管的高电压半导体器件具有改进的性能，包括降低的导通状态电阻。 该器件包括在源区和漏区之间具有漂移区的半导体衬底。 漂移区域包括具有在源极区域和漏极区域之间延伸的间隔开的沟槽电容器的结构和在源极区域和漏极区域之间延伸的垂直叠层。 当器件处于导通状态时，电流在源区和漏区之间流动; 并且当器件处于截止/截止状态时，漂移区被耗尽到堆栈中。

    PN junction and MOS capacitor hybrid RESURF transistor
    9.
    发明授权
    PN junction and MOS capacitor hybrid RESURF transistor 有权
    PN结和MOS电容混合RESURF晶体管

    公开(公告)号：US07795671B2

    公开(公告)日：2010-09-14

    申请号：US11619671

    申请日：2007-01-04

    申请人： Steven Leibiger ,  Gary Dolny

    发明人： Steven Leibiger ,  Gary Dolny

    IPC分类号： H01L27/108

    CPC分类号： H01L29/7835 ,  H01L27/088 ,  H01L27/0927 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/66659

    摘要： A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors. When the device is in an on state, current flows between the source and drain regions through the second region of the second conductivity type; and, when the device is in an off/blocking state, the second conductivity region is depleted four ways into the first and third regions of the stack and into the first and second trench capacitors.

    摘要翻译： 诸如RESURF晶体管的高电压半导体器件具有改进的性能，包括降低的导通状态电阻。 该器件包括半导体衬底; 设置在基板中的源极区域和漏极区域; 其中所述源极区域和所述漏极区域彼此横向间隔开; 以及在源极区域和漏极区域之间的衬底中的漂移区域。 漂移区域包括具有在源极区域和漏极区域之间延伸的至少两个隔开的沟槽电容器的结构; 并且还包括具有至少第一导电类型的第一区域，第二导电类型的第二区域和第一导电类型的第三区域的堆叠，其中所述堆叠在所述源极区域和所述漏极区域之间以及 所述至少第一和第二沟槽电容器并与第一和第二沟槽电容器电连接。 当器件处于导通状态时，电流通过第二导电类型的第二区域在源区和漏区之间流动; 并且当器件处于截止/截止状态时，第二导电区域耗尽四个方式进入堆叠的第一和第三区域以及第一和第二沟槽电容器。