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    DMOS device with sealed channel processing
    1.
    发明授权
    DMOS device with sealed channel processing 有权
    DMOS设备密封通道处理

    公开(公告)号：US07407851B2

    公开(公告)日：2008-08-05

    申请号：US11386316

    申请日：2006-03-22

    申请人： Gayle W. Miller ,  Irwin D. Rathbun ,  Stefan Schwantes ,  Michael Graf ,  Volker Dudek

    发明人： Gayle W. Miller ,  Irwin D. Rathbun ,  Stefan Schwantes ,  Michael Graf ,  Volker Dudek

    IPC分类号： H01L21/8238 ,  H01L21/38

    CPC分类号： H01L21/2253 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

    摘要翻译： 一种制造电子设备的方法和由此产生的电子设备。 该方法包括在衬底上形成衬垫氧化物层，在衬垫氧化物层上形成氮化硅层，并在氮化硅层上形成顶部氧化物层。 然后在衬底的第一部分中形成第一掺杂区域。 除去顶部氧化物层的第一部分; 使用顶部氧化物层的剩余部分来对准第二掺杂剂掩模，并且形成第二掺杂剂区域。 退火步骤驱动掺杂剂，但是氧化物扩散到衬底受到氮化硅层的限制; 因此，氮化硅层确保在退火步骤之后，在靠近掺杂剂区域的区域中硅的最上表面基本上是平面的。

    DMOS DEVICE WITH SEALED CHANNEL PROCESSING
    2.
    发明申请
    DMOS DEVICE WITH SEALED CHANNEL PROCESSING 审中-公开
    具有密封通道加工的DMOS器件

    公开(公告)号：US20080290426A1

    公开(公告)日：2008-11-27

    申请号：US12185744

    申请日：2008-08-04

    申请人： Gayle W. Miller ,  Irwin D. Rathbun ,  Stefan Schwantes ,  Michael Graf ,  Volker Dudek

    发明人： Gayle W. Miller ,  Irwin D. Rathbun ,  Stefan Schwantes ,  Michael Graf ,  Volker Dudek

    IPC分类号： H01L21/00

    CPC分类号： H01L21/2253 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

    摘要翻译： 一种制造电子设备的方法和由此产生的电子设备。 该方法包括在衬底上形成衬垫氧化物层，在衬垫氧化物层上形成氮化硅层，并在氮化硅层上形成顶部氧化物层。 然后在衬底的第一部分中形成第一掺杂区域。 除去顶部氧化物层的第一部分; 使用顶部氧化物层的剩余部分来对准第二掺杂剂掩模，并且形成第二掺杂剂区域。 退火步骤驱动掺杂剂，但是氧化物扩散到衬底受到氮化硅层的限制; 因此，氮化硅层确保在退火步骤之后，在靠近掺杂剂区域的区域中硅的最上表面基本上是平面的。

    Method And Manufacturing Low Leakage Mosfets And FinFets
    7.
    发明申请
    Method And Manufacturing Low Leakage Mosfets And FinFets 有权
    方法和制造低漏磁和FinFets

    公开(公告)号：US20110260250A1

    公开(公告)日：2011-10-27

    申请号：US13174398

    申请日：2011-06-30

    申请人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

    发明人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

    IPC分类号： H01L29/78

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

    摘要： By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

    摘要翻译： 通过将晶片的主平面与（100）平面而不是（110）平面对准，可以沿着（100）平面流动的初级电流形成器件。 在这种情况下，设备将以大约54.7度与（111）平面相交。 这个相交角度可以显着地减少沿（111）方向的应力传播/释放，从而减少缺陷以及泄漏和寄生电流。 泄漏电流降低是短路源极 - 漏极结所需的位错长度变化的直接后果。 通过使用这种技术，对于N沟道CMOS器件，泄漏电流降低高达两个数量级。

    REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
    8.
    发明申请
    REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION 审中-公开
    使用自对准TRENCH隔离的减少电场DMOS

    公开(公告)号：US20080173940A1

    公开(公告)日：2008-07-24

    申请号：US12018721

    申请日：2008-01-23

    申请人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

    发明人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7824 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

    摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

    摘要翻译： 一种制造电子装置的方法和所得到的电子装置。 该方法包括在绝缘体上硅衬底的最上侧形成栅极氧化物; 在所述栅极氧化物上形成第一多晶硅层; 以及在所述第一多晶硅层上形成第一二氧化硅层。 然后在第一二氧化硅层上形成第一氮化硅层，接着形成第二二氧化硅层。 通过所有以前的介电层蚀刻浅沟槽并进入SOI衬底。 蚀刻的沟槽用另一介质层（例如二氧化硅）填充并平坦化。 去除每个前述电介质层，留下电介质层的最上面的侧壁区域暴露以与稍后施加的多晶硅栅极区域接触。 侧壁区域的形成确保全场氧化物厚度，从而产生具有减小的电场和栅极和漂移区域之间的减小的电容的器件。

    Low leakage FINFETs
    9.
    发明授权
    Low leakage FINFETs 有权
    低泄漏FINFET

    公开(公告)号：US08378414B2

    公开(公告)日：2013-02-19

    申请号：US13174398

    申请日：2011-06-30

    申请人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

    发明人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

    摘要： By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

    摘要翻译： 通过将晶片的主平面与（100）平面而不是（110）平面对准，可以沿着（100）平面流动的初级电流形成器件。 在这种情况下，设备将在（111）平面上以大约54.7度相交。 这个相交角度可以显着地减少沿（111）方向的应力传播/释放，从而减少缺陷以及泄漏和寄生电流。 泄漏电流降低是短路源极 - 漏极结所需的位错长度变化的直接后果。 通过使用这种技术，对于N沟道CMOS器件，泄漏电流降低高达两个数量级。

    REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
    10.
    发明申请
    REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION 审中-公开

    公开(公告)号：US20080135933A1

    公开(公告)日：2008-06-12

    申请号：US12018744

    申请日：2008-01-23

    申请人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

    发明人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

    IPC分类号： H01L29/786

    CPC分类号： H01L29/7824 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

    摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.