公开(公告)号：US07626878B1

公开(公告)日：2009-12-01

申请号：US11838818

申请日：2007-08-14

申请人： Hwong-Kwo Lin ,  Ge Yang ,  Ethan A. Frazier ,  Charles Chew-Yuen Young

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Ethan A. Frazier ,  Charles Chew-Yuen Young

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C11/413

摘要： One embodiment of the present invention sets forth an active bit line charge keeper circuit for improving the reliability of a static random access memory (SRAM) circuit. The active bit line charge keeper circuit includes two sub-circuits, each disposed between bit line pairs within the SRAM circuit. The first sub-circuit mitigates residual state associated with over-developed read state on the bit lines. The second sub-circuit mitigates the effects of residual state associated with reading one value on a given pair of bit lines and subsequently writing a different value. By mitigating the effects of residual state within an SRAM circuit, higher reliability at a given performance level may be achieved.

摘要翻译： 本发明的一个实施例提出了一种用于提高静态随机存取存储器（SRAM）电路的可靠性的有源位线电荷保持器电路。 有源位线电荷保持电路包括两个子电路，每个子电路设置在SRAM电路内的位线对之间。 第一个子电路减轻了与位线上的超显影读取状态相关联的残余状态。 第二子电路减轻与给定的一对位线读取一个值相关联的残余状态的影响，并随后写入不同的值。 通过减轻SRAM电路中的残留状态的影响，可以在给定的性能水平下实现更高的可靠性。

公开(公告)号：US20090045847A1

公开(公告)日：2009-02-19

申请号：US11838171

申请日：2007-08-13

申请人： Hwong-Kwo Lin ,  Ge Yang ,  Ethan A. Frazier ,  Charles Chew-Yuen Young

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Ethan A. Frazier ,  Charles Chew-Yuen Young

IPC分类号： H03K19/00

CPC分类号： G04F5/00 ,  H03K5/133 ,  H03K2005/00058

摘要： One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

摘要翻译： 本发明的一个实施例提出了一组用于设计用于集成电路的灵活定时发生器的构建块电路。 第一和第二构造块包括在制造之前可以定制和微调的延迟元件。 第三构建块可以在制造之前以及制造之后进行调整。 三个构建块可以并入模块化架构，使设计人员能够轻松地生成良好表征的，灵活的通用定时器电路。

公开(公告)号：US07839170B1

公开(公告)日：2010-11-23

申请号：US12404183

申请日：2009-03-13

申请人： Ge Yang ,  Hwong-Kwo Lin ,  Charles Chew-Yuen Young

发明人： Ge Yang ,  Hwong-Kwo Lin ,  Charles Chew-Yuen Young

IPC分类号： H03K19/0175 ,  H03L5/00

CPC分类号： H03K3/356182

摘要： One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from a low voltage domain to a high voltage domain, where VDDH is the supply voltage of the high voltage domain and VDDL is the supply voltage of the low voltage domain. A level shifting circuit uses a single input rather than dual rail inputs and does not produce a direct current flow in order to reduce the power consumption. The voltage level shifting circuit may also be used to shift a clock signal since the delays of the rising and falling edges of the clock signal are matched by using a delay element.

摘要翻译： 本发明的一个实施例提出了一种用于将信号从低电压域的电压电平移位到高电压域的技术，其中VDDH是高电压域的电源电压，而VDDL是低电压域的电源电压 。 电平移位电路使用单个输入而不是双轨输入，并且不产生直流电流以便降低功耗。 由于时钟信号的上升沿和下降沿的延迟通过使用延迟元件来匹配，电压电平移位电路也可以用于移位时钟信号。

公开(公告)号：US07768320B1

公开(公告)日：2010-08-03

申请号：US11943455

申请日：2007-11-20

申请人： Ge Yang ,  Hwong-Kwo Lin ,  Charles Chew-Yuen Young

发明人： Ge Yang ,  Hwong-Kwo Lin ,  Charles Chew-Yuen Young

IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC分类号： G11C7/02 ,  G11C7/065 ,  G11C7/067

摘要： One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.

摘要翻译： 本发明的一个实施例提出了一种容忍工艺变化的读出放大器触发器设计。 通过读出放大器触发电路的信号转换的特定分级消除了涉及互补对称金属中的n沟道场效应晶体管（N-FET）和p沟道场效应晶体管（P-FET）之间涉及短路电流的操作阶段 氧化物半导体工艺。 通过消除读出放大器触发器内的N-FET和P-FET之间的短路电流，可以通过读出放大器触发器容忍N-FET和P-FET之间的大的电导率变化。 这种电导率比容差转换为读出放大器触发电路对工艺变化的容差。

公开(公告)号：US07583126B2

公开(公告)日：2009-09-01

申请号：US11753501

申请日：2007-05-24

申请人： Ge Yang ,  Hwong-Kwo Lin ,  Charles Chew-Yuen Young

发明人： Ge Yang ,  Hwong-Kwo Lin ,  Charles Chew-Yuen Young

IPC分类号： H03L5/00

CPC分类号： H03K3/356104

摘要： An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down.

摘要翻译： 提供了一种用于在低电压域断电时防止电流泄漏或直流电的装置和方法。 包括连接在低电压域和高电压域之间的电压转换电路。 这种电压转换电路包括用于在低电压域断电时防止电流泄漏的电路部件。

公开(公告)号：US07504872B2

公开(公告)日：2009-03-17

申请号：US11838171

申请日：2007-08-13

申请人： Hwong-Kwo Lin ,  Ge Yang ,  Ethan A. Frazier ,  Charles Chew-Yuen Young

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Ethan A. Frazier ,  Charles Chew-Yuen Young

IPC分类号： H03H11/26 ,  G06F7/38 ,  H03K19/173

CPC分类号： G04F5/00 ,  H03K5/133 ,  H03K2005/00058

摘要： One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

摘要翻译： 本发明的一个实施例提出了一组用于设计用于集成电路的灵活定时发生器的构建块电路。 第一和第二构造块包括在制造之前可以定制和微调的延迟元件。 第三构建块可以在制造之前以及制造之后进行调整。 三个构建块可以并入模块化架构，使设计人员能够轻松地生成良好表征的，灵活的通用定时器电路。

公开(公告)号：US07772885B1

公开(公告)日：2010-08-10

申请号：US12467112

申请日：2009-05-15

申请人： Hwong-Kwo Lin ,  Ge Yang ,  Guoqing Ning ,  Charles Chew-Yuen Young

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Guoqing Ning ,  Charles Chew-Yuen Young

IPC分类号： H03K19/0175

CPC分类号： H03K3/356113

摘要： One embodiment of the present invention sets forth a technique for shifting the voltage level of signals from the high voltage domain to a low voltage domain, where VDD_IO is the supply voltage of the high voltage domain and VDD_Logic is the supply voltage of the low voltage domain. A level shifting circuit using a combination of I/O and logic transistors avoids exceeding a maximum tolerable voltage across the gate and source of any of the transistors. The level shifting circuit operates includes a reference voltage circuit that is independent of VDD_IO, so the same level shifting circuit may be used for various VDD_IO voltages. Additionally, the voltage level shifting circuit is not sensitive to scaling of VDD_Logic and operates properly when VDD_Logic is reduced due to shrinking silicon process technology and/or is reduced for a low power application.

摘要翻译： 本发明的一个实施例提出了一种用于将来自高电压域的信号的电压电平移位到低电压域的技术，其中VDD_IO是高电压域的电源电压，而VDD_Logic是低电压域的电源电压 。 使用I / O和逻辑晶体管的组合的电平移动电路避免超过任何晶体管的栅极和源极上的最大容许电压。 电平移位电路操作包括独立于VDD_IO的参考电压电路，因此相同的电平移位电路可用于各种VDD_IO电压。 此外，电压电平移位电路对VDD_Logic的缩放不敏感，并且由于硅工艺技术的缩小而降低了VDD_Logic并且/或者为了降低功耗，所以可以正常工作。

公开(公告)号：US07492204B1

公开(公告)日：2009-02-17

申请号：US11838172

申请日：2007-08-13

申请人： Hwong-Kwo Lin ,  Ge Yang ,  Ethan A. Frazier ,  Charles Chew-Yuen Young

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Ethan A. Frazier ,  Charles Chew-Yuen Young

IPC分类号： H03H11/26 ,  G06F7/38 ,  H03K19/173

CPC分类号： H03K5/131 ,  H03K2005/00039 ,  H03K2005/00058

摘要： One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

公开(公告)号：US20080290935A1

公开(公告)日：2008-11-27

申请号：US11753501

申请日：2007-05-24

申请人： Ge Yang ,  Hwong-Kwo Lin ,  Charles Chew-Yuen Young

发明人： Ge Yang ,  Hwong-Kwo Lin ,  Charles Chew-Yuen Young

IPC分类号： G05F1/10

CPC分类号： H03K3/356104

摘要： An apparatus and method are provided for preventing a current leakage or direct current when a low voltage domain is powered down. Included is a voltage transition circuit connected between a low voltage domain and a high voltage domain. Such voltage transition circuit includes a circuit component for preventing a current leakage when the low voltage domain is powered down.

摘要翻译： 提供了一种用于在低电压域断电时防止电流泄漏或直流电的装置和方法。 包括连接在低电压域和高电压域之间的电压转换电路。 这种电压转换电路包括用于在低电压域断电时防止电流泄漏的电路部件。

公开(公告)号：US07830175B1

公开(公告)日：2010-11-09

申请号：US12269200

申请日：2008-11-12

申请人： Hwong-Kwo Lin ,  Ge Yang ,  Charles Chew-Yuen Young

发明人： Hwong-Kwo Lin ,  Ge Yang ,  Charles Chew-Yuen Young

IPC分类号： H03K19/0175 ,  H03L5/00

CPC分类号： H03K3/35613

摘要： An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.

摘要翻译： 一种装置包括连接到低电压域的单轨输入和连接到单轨输入的电压转换电路。 电压转换电路被配置为将经由单轨输入接收的低压域的电压转换为高电压域的电压。