公开(公告)号：US20080145998A1

公开(公告)日：2008-06-19

申请号：US11531493

申请日：2006-09-13

申请人： GERARDO A. DELGADINO ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

发明人： GERARDO A. DELGADINO ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC分类号： H01L21/76

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

摘要翻译： 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔是 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。

公开(公告)号：US07435685B2

公开(公告)日：2008-10-14

申请号：US11531493

申请日：2006-09-13

申请人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

发明人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li Huang ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC分类号： H01L21/311

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

摘要翻译： 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。

公开(公告)号：US07132369B2

公开(公告)日：2006-11-07

申请号：US10745344

申请日：2003-12-22

申请人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

发明人： Gerardo A. Delgadino ,  Yan Ye ,  Neungho Shin ,  Yunsang Kim ,  Li-Qun Xia ,  Tzu-Fang Huang ,  Lihua Li ,  Joey Chiu ,  Xiaoye Zhao ,  Fang Tian ,  Wen Zhu ,  Ellie Yieh

IPC分类号： H01L21/302

CPC分类号： H01L21/76826 ,  H01L21/76811 ,  H01L21/76813

摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

摘要翻译： 一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。

公开(公告)号：US20050026430A1

公开(公告)日：2005-02-03

申请号：US10632873

申请日：2003-08-01

申请人： Yunsang Kim ,  Neungho Shin ,  Heeyeop Chae ,  Joey Chiu ,  Yan Ye ,  Fang Tian ,  Xiaoye Zhao

发明人： Yunsang Kim ,  Neungho Shin ,  Heeyeop Chae ,  Joey Chiu ,  Yan Ye ,  Fang Tian ,  Xiaoye Zhao

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31116 ,  Y10S438/963

摘要： The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 Å/min.

摘要翻译： 本发明包括使用等离子体蚀刻室中的气体混合物的等离子体来选择性地蚀刻在衬底上形成的低k电介质材料的方法。 气体混合物包括富氟碳氟化合物或氢氟烃气体，含氮气体和一种或多种添加剂气体，例如富氢氢氟烃气体，惰性气体和/或碳 - 氧气体。 该方法提供了大于约5:1的光致抗蚀剂掩模蚀刻选择比的低k电介质，大于10:1的低k电介质到阻挡层/衬层蚀刻选择比，以及低k电介质蚀刻速率 高于约4000Å/ min。

公开(公告)号：US07256134B2

公开(公告)日：2007-08-14

申请号：US10632873

申请日：2003-08-01

申请人： Yunsang Kim ,  Neungho Shin ,  Heeyeop Chae ,  Joey Chiu ,  Yan Ye ,  Fang Tian ,  Xiaoye Zhao

发明人： Yunsang Kim ,  Neungho Shin ,  Heeyeop Chae ,  Joey Chiu ,  Yan Ye ,  Fang Tian ,  Xiaoye Zhao

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  Y10S438/963

摘要： The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 Å/min.

摘要翻译： 本发明包括使用等离子体蚀刻室中的气体混合物的等离子体来选择性地蚀刻形成在衬底上的低k电介质材料的方法。 气体混合物包括富氟碳氟化合物或氢氟烃气体，含氮气体和一种或多种添加剂气体，例如富氢氢氟烃气体，惰性气体和/或碳 - 氧气体。 该方法提供了大于约5:1的光致抗蚀剂掩模蚀刻选择比的低k电介质，大于10:1的低k电介质到阻挡层/衬层蚀刻选择比，以及低k电介质蚀刻速率 高于约4000Å/ min。