公开(公告)号：US07236410B2

公开(公告)日：2007-06-26

申请号：US11169106

申请日：2005-06-27

申请人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Vivek K. De

发明人： Gerhard Schrom ,  Fabrice Paillet ,  Tanay Karnik ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Vivek K. De

IPC分类号： G11C7/00 ,  G11C17/00 ,  G11C5/06

CPC分类号： G11C17/18

摘要： A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

摘要翻译： 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。

公开(公告)号：US07167397B2

公开(公告)日：2007-01-23

申请号：US11158518

申请日：2005-06-21

申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De ,  Tanay Karnik

发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Mohsen Alavi ,  Vivek K. De ,  Tanay Karnik

IPC分类号： G11C16/04

CPC分类号： G11C17/18

摘要： A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

摘要翻译： 提供了一种对存储器阵列进行编程的方法，包括通过相对于各个字线相互依次提供多个电压步骤来访问存储器阵列的多个字线，以及每个存储器阵列的多个位线 访问相应字线的时间，对与同时访问的各个字和位线相对应的多个设备进行编程，每个设备通过断开设备的介电层进行编程，访问位线被排序，使得只有 一个设备中的单个设备一次被编程。

公开(公告)号：US07230846B2

公开(公告)日：2007-06-12

申请号：US11151982

申请日：2005-06-14

申请人： Ali Keshavarzi ,  Stephen H Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M Khellah ,  Yibin Ye ,  Vivek K De ,  Gerhard Schrom

发明人： Ali Keshavarzi ,  Stephen H Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M Khellah ,  Yibin Ye ,  Vivek K De ,  Gerhard Schrom

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C2211/4016

摘要： In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

摘要翻译： 通常，在一个方面，本公开描述了包括以行和列布置的多个存储单元的存储器阵列。 每个存储单元包括具有能够存储电荷的浮动体的晶体管。 多个字线和清除线与存储器单元的行互连。 多个位线被连接到存储器单元的列。 通过字线提供的驱动信号，清除线和位线可以协作以改变一个或多个存储器单元中的浮体区域的电荷。

公开(公告)号：US07075821B2

公开(公告)日：2006-07-11

申请号：US10956407

申请日：2004-09-30

申请人： Yibin Ye ,  Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Gerhard Schrom ,  Vivek K. De

发明人： Yibin Ye ,  Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Gerhard Schrom ,  Vivek K. De

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C2211/4016

摘要： A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.

公开(公告)号：US07355246B2

公开(公告)日：2008-04-08

申请号：US11268430

申请日：2005-11-07

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L29/76

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

公开(公告)号：US07321502B2

公开(公告)日：2008-01-22

申请号：US10956285

申请日：2004-09-30

申请人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Alavi Mohsen ,  Vivek K. De

发明人： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Alavi Mohsen ,  Vivek K. De

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.

摘要翻译： 描述了一种在驱动电流通过电容器的同时在电容器的电介质材料内感应电介质击穿的方法。 电流特定于正在写入电容器的数据。 该方法还涉及通过解释由电容器电阻确定的电容器的行为来读取数据，其中电容器的电阻是诱导和驱动的结果。

公开(公告)号：US06992339B2

公开(公告)日：2006-01-31

申请号：US10750572

申请日：2003-12-31

申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： H01L27/10

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7841

摘要： Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

公开(公告)号：US06906973B1

公开(公告)日：2005-06-14

申请号：US10746148

申请日：2003-12-24

申请人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12

摘要： Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.

摘要翻译： 一些实施例使用预充电器件将耦合到存储器单元的位线预充电至参考电压，基于存储器单元存储的值，放电期间的注入，放电期间的位线放电， 使用预充电器件进入位线的第一电流，以及在放电期间使用第二预充电器件将第二电流注入参考位线。 此外，在放电期间，在位线上的电压和参考位线上的电压之间感测到差异。

公开(公告)号：US07102358B2

公开(公告)日：2006-09-05

申请号：US10880337

申请日：2004-06-29

申请人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H Tang ,  Mohsen Alavi ,  Vivek K De

发明人： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad M Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H Tang ,  Mohsen Alavi ,  Vivek K De

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R19/16571

摘要： A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.

摘要翻译： 由于过电压状态，晶体管可能具有劣化特性。 可以感测劣化特性以确定晶体管先前已经经受过压状态。

公开(公告)号：US07072205B2

公开(公告)日：2006-07-04

申请号：US10716755

申请日：2003-11-19

申请人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C11/24 ,  G11C11/34

CPC分类号： G11C11/4094 ,  G11C11/404 ,  G11C11/4076 ,  G11C11/4085

摘要： A row of floating-body single transistor memory cells is written to in two phases.

摘要翻译： 一行浮体单晶体管存储单元分两个阶段写入。