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公开(公告)号：US06615341B2
公开(公告)日：2003-09-02
申请号：US09876189
申请日：2001-06-05
申请人： Gilbert C. Sih , Qiuzhen Zou , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee , Charles E. Sakamaki , Prashant A. Kantak , Sanjay K. Jha , Jian Lin
发明人： Gilbert C. Sih , Qiuzhen Zou , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee , Charles E. Sakamaki , Prashant A. Kantak , Sanjay K. Jha , Jian Lin
IPC分类号： G06F9302
CPC分类号： G06F9/3816 , G06F9/30014 , G06F9/30098 , G06F9/30149 , G06F9/30152 , G06F9/3885 , G06F15/7857
摘要： A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.
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2.发明授权Application specific integrated circuit (ASIC) for performing rapid speech compression in a mobile telephone system 失效专用集成电路（ASIC），用于在移动电话系统中执行快速语音压缩
公开(公告)号：US5784532A
公开(公告)日：1998-07-21
申请号：US197417
申请日：1994-02-16
申请人： John G. McDonough , Chienchung Chang , Randeep Singh , Charles E. Sakamaki , Ming-Chang Tsai , Prashant Kantak
发明人： John G. McDonough , Chienchung Chang , Randeep Singh , Charles E. Sakamaki , Ming-Chang Tsai , Prashant Kantak
IPC分类号： G10L19/08 , G06F5/01 , G10L19/00 , G10L19/04 , G10L19/06 , G10L19/12 , G10L19/14 , H03M7/30 , G10L9/00
摘要： A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is provided. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further comprises a specifically designed block normalization circuitry.
摘要翻译： 提供了一种在专用集成电路（ASIC）中实现声码器的方法和装置。 该装置包含根据简化指令集（RISC）架构执行计算的DSP内核。 该电路还包括被称为最小化处理器的被专门设计的到DSP核的从属处理器。 该装置还包括专门设计的块归一化电路。
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公开(公告)号：US5727123A
公开(公告)日：1998-03-10
申请号：US575303
申请日：1995-12-20
申请人： John G. McDonough , Chienchung Chang , Randeep Singh , Charles E. Sakamaki , Ming-Chang Tsai , Prashant Kantak
发明人： John G. McDonough , Chienchung Chang , Randeep Singh , Charles E. Sakamaki , Ming-Chang Tsai , Prashant Kantak
IPC分类号： G10L19/08 , G06F5/01 , G10L19/00 , G10L19/04 , G10L19/06 , G10L19/12 , G10L19/14 , H03M7/30 , G10L3/00
摘要： A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is provided. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further comprises a specifically designed block normalization circuitry.
摘要翻译： 提供了一种在专用集成电路（ASIC）中实现声码器的方法和装置。 该装置包含根据简化指令集（RISC）架构执行计算的DSP内核。 该电路还包括被称为最小化处理器的被专门设计的到DSP核的从属处理器。 该装置还包括专门设计的块归一化电路。
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4.发明授权Cached memory system and cache controller for embedded digital signal processor 有权用于嵌入式数字信号处理器的缓存存储系统和缓存控制器公开(公告)号：US08316185B2
公开(公告)日：2012-11-20
申请号：US12792865
申请日：2010-06-03
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/08 , G06F12/0857 , G06F12/0897 , G06F2212/251 , G06F2212/253
摘要： A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
摘要翻译： 描述了可以处理高速率输入数据并确保嵌入式DSP能够满足实时约束的高速缓存存储器系统。 缓存的存储器系统包括位于处理器核心附近的高速缓存存储器，处于下一较高存储器级别的片上存储器以及最高存储器级别的外部主存储器。 缓存控制器处理高速缓冲存储器和片上存储器之间的指令和数据的分页用于高速缓存未命中。 直接存储交换（DME）控制器处理片上存储器和外部存储器之间的用户控制的寻呼。 用户/程序员可以安排在处理器核心实际需要之前将处理器核心所需的指令和数据存储在片上存储器中。
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5.发明申请Cached Memory System and Cache Controller for Embedded Digital Signal Processor 有权用于嵌入式数字信号处理器的缓存存储系统和缓存控制器公开(公告)号：US20100235578A1
公开(公告)日：2010-09-16
申请号：US12792865
申请日：2010-06-03
CPC分类号： G06F12/0811 , G06F12/08 , G06F12/0857 , G06F12/0897 , G06F2212/251 , G06F2212/253
摘要： A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
摘要翻译： 描述了可以处理高速率输入数据并确保嵌入式DSP能够满足实时约束的高速缓存存储器系统。 缓存的存储器系统包括位于处理器核心附近的高速缓存存储器，处于下一较高存储器级别的片上存储器以及最高存储器级别的外部主存储器。 缓存控制器处理高速缓冲存储器和片上存储器之间的指令和数据的分页用于高速缓存未命中。 直接存储交换（DME）控制器处理片上存储器和外部存储器之间的用户控制的寻呼。 用户/程序员可以安排在处理器核心实际需要之前将处理器核心所需的指令和数据存储在片上存储器中。
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6.发明授权Cached memory system and cache controller for embedded digital signal processor 有权用于嵌入式数字信号处理器的缓存存储系统和缓存控制器公开(公告)号：US07769950B2
公开(公告)日：2010-08-03
申请号：US10807648
申请日：2004-03-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/08 , G06F12/0857 , G06F12/0897 , G06F2212/251 , G06F2212/253
摘要： A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
摘要翻译： 描述了可以处理高速率输入数据并确保嵌入式DSP能够满足实时约束的高速缓存存储器系统。 缓存的存储器系统包括位于处理器核心附近的高速缓存存储器，处于下一较高存储器级别的片上存储器以及最高存储器级别的外部主存储器。 缓存控制器处理高速缓冲存储器和片上存储器之间的指令和数据的分页用于高速缓存未命中。 直接存储交换（DME）控制器处理片上存储器和外部存储器之间的用户控制的寻呼。 用户/程序员可以安排在处理器核心实际需要之前将处理器核心所需的指令和数据存储在片上存储器中。
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