公开(公告)号：US06615341B2

公开(公告)日：2003-09-02

申请号：US09876189

申请日：2001-06-05

申请人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

发明人： Gilbert C. Sih ,  Qiuzhen Zou ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee ,  Charles E. Sakamaki ,  Prashant A. Kantak ,  Sanjay K. Jha ,  Jian Lin

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

公开(公告)号：US06425070B1

公开(公告)日：2002-07-23

申请号：US09044086

申请日：1998-03-18

申请人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee

发明人： Qiuzhen Zou ,  Gilbert C. Sih ,  Inyup Kang ,  Quaeed Motiwala ,  Deepu John ,  Li Zhang ,  Haitao Zhang ,  Way-Shing Lee

IPC分类号： G06F9302

CPC分类号： G06F9/3816 ,  G06F9/30014 ,  G06F9/30098 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/3885 ,  G06F15/7857

摘要： The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.

摘要翻译： 本发明是用于数字信号处理的新颖且改进的方法和电路。 本发明的一个方面要求使用可变长度指令集。 可变长度指令的一部分可以存储在存储器空间内的相邻位置，同时跨越存储器字边界的指令的开始和结束。 此外，通过使指令包含可变数量的指令片段来实现本发明的附加方面。 每个指令片段导致执行特定操作或操作，允许在每个时钟周期期间进行多个操作。 因此，在每个时钟周期期间执行多个操作，减少执行任务所需的总时钟周期数。 示例性DSP包括一组三个数据总线，数据可以通过该数据总线与寄存器组和三个数据存储器交换。 使用两条以上的数据总线，特别是三条数据总线，实现了本发明的另一方面，这显着减少了总线竞争。 本发明的一个实施例要求数据总线包括一个宽的总线和两个窄的总线。 宽总线耦合到宽数据存储器，并且两个窄总线耦合到两个窄数据存储器。 通过使用具有可由至少两个处理单元访问的寄存器的寄存器组来实现本发明的另一方面。 这允许通过多个处理单元对特定数据集执行多个操作，而不向存储器读取和写入数据。 本发明的示例性实施例中的处理单元包括算术逻辑（ALU）和乘法累加（MAC）单元。 当结合使用多总线架构，高度并行指令或两者时，实现本发明的另一方面，其中执行高度流水线化，多操作的处理。

公开(公告)号：US06594303B1

公开(公告)日：2003-07-15

申请号：US09228470

申请日：1999-01-11

申请人： Avneesh Agrawal ,  Paul E. Bender ,  Luca Blessent ,  Brian K. Butler ,  Quaeed Motiwala

发明人： Avneesh Agrawal ,  Paul E. Bender ,  Luca Blessent ,  Brian K. Butler ,  Quaeed Motiwala

IPC分类号： H04B169

CPC分类号： H04B1/707 ,  H04B2201/70701

摘要： Techniques for coherent demodulation in the presence of phase discontinuities is described. In the exemplary embodiment, times when phase discontinuities occur are known apriori by a receiver in which demodulation is being performed. In an alternate embodiment, the discontinuity location is signaled to the receiver in advance by the transmitter which generates the signals being demodulated. A pilot signal is prepared for optimal coherent demodulation by the use of two filters: one capable of withstanding the effects of phase discontinuity; a second providing superior filtering performance than the first so long as phase discontinuities are not present. Both filters are simultaneously operated. However, the superior performing filter is selected for use in demodulation whenever possible.

摘要翻译： 描述了存在相位不连续性的相干解调技术。 在示例性实施例中，发生相位不连续性的时间是正在执行解调的接收机所知道的。 在替代实施例中，不连续位置由产生被解调的信号的发射机预先发送给接收机。 通过使用两个滤波器来准备导频信号以实现最佳相干解调：一个能够承受相位不连续性的影响; 只要不存在相位不连续性，第二个提供比第一个优越的滤波性能。 两个过滤器同时运行。 然而，优选执行滤波器被选择用于解调，只要可能。

公开(公告)号：US07471657B2

公开(公告)日：2008-12-30

申请号：US09934091

申请日：2001-08-20

申请人： Luca Blessent ,  Quaeed Motiwala

发明人： Luca Blessent ,  Quaeed Motiwala

IPC分类号： H04B7/216

CPC分类号： H04W52/20 ,  H04B1/7113 ,  H04B2201/70701 ,  H04L25/0224 ,  H04L2027/0046 ,  H04L2027/0065 ,  H04L2027/0093 ,  H04W52/143

摘要： The punctured pilot channel comprises information symbols of uncertain sign punctured into a sequence of pilot channel symbols of predetermined sign. The apparatus includes an information sign demodulation circuit for determining the sign of the information symbols in response to the pilot channel symbols. A continuous pilot generator generates a non-punctured pilot channel of predetermined sign from the information symbols and the pilot channel symbols. In a first embodiment, the information sign demodulator further comprises a dot product circuit for calculating a dot product of the pilot channel symbols and the punctured information symbols, and a threshold comparator for comparing the dot product to a predetermined threshold.

摘要翻译： 穿孔导频信道包括穿入预定符号的导频信道符号序列的不确定符号的信息符号。 该装置包括用于响应于导频信道符号确定信息符号的符号的信息符号解调电路。 连续导频发生器从信息符号和导频信道符号生成预定符号的未穿孔导频信道。 在第一实施例中，信息符号解调器还包括用于计算导频信道符号和穿孔信息符号的点积的点积电路，以及用于将点乘积与预定阈值进行比较的阈值比较器。

公开(公告)号：US07590164B2

公开(公告)日：2009-09-15

申请号：US09766558

申请日：2001-01-19

申请人： Quaeed Motiwala ,  Christopher C. Riddle ,  Luca Blessent ,  Shih-Yi Yeh ,  Robert J. Fuchs

发明人： Quaeed Motiwala ,  Christopher C. Riddle ,  Luca Blessent ,  Shih-Yi Yeh ,  Robert J. Fuchs

IPC分类号： H04B1/00

CPC分类号： H04B1/7117 ,  H04B7/2659 ,  H04B2201/70707

摘要： The frame of data is partitioned into a plurality of portions of data symbols. A plurality of channel elements is assigned to demodulate data symbols of correspondingly the plurality of portions of data symbols. The number of the plurality of portions of data symbols is higher in a case at high data rate than a case at low data rate.

摘要翻译： 数据帧被划分成多个数据符号部分。 分配多个信道单元以解调对应于数据符号的多个部分的数据符号。 在高数据速率的情况下，数据符号的多个部分的数量比在低数据速率的情况下更高。

公开(公告)号：US06304563B1

公开(公告)日：2001-10-16

申请号：US09298394

申请日：1999-04-23

申请人： Luca Blessent ,  Quaeed Motiwala

发明人： Luca Blessent ,  Quaeed Motiwala

IPC分类号： H04B7216

CPC分类号： H04W52/20 ,  H04B1/7113 ,  H04B2201/70701 ,  H04L25/0224 ,  H04L2027/0046 ,  H04L2027/0065 ,  H04L2027/0093 ,  H04W52/143

摘要： The punctured pilot channel comprises information symbols of uncertain sign punctured into a sequence of pilot channel symbols of predetermined sign. The apparatus includes an information sign demodulation circuit for determining the sign of the information symbols in response to the pilot channel symbols. A continuous pilot generator generates a non-punctured pilot channel of predetermined sign from the information symbols and the pilot channel symbols. In a first embodiment, the information sign demodulator further comprises a dot product circuit for calculating a dot product of the pilot channel symbols and the punctured information symbols, and a threshold comparator for comparing the dot product to a predetermined threshold.

摘要翻译： 穿孔导频信道包括穿入预定符号的导频信道符号序列的不确定符号的信息符号。 该装置包括用于响应于导频信道符号确定信息符号的符号的信息符号解调电路。 连续导频发生器从信息符号和导频信道符号生成预定符号的未穿孔导频信道。 在第一实施例中，信息符号解调器还包括用于计算导频信道符号和穿孔信息符号的点积的点积电路，以及用于将点乘积与预定阈值进行比较的阈值比较器。