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公开(公告)号：US11164881B2
公开(公告)日：2021-11-02
申请号：US16127262
申请日：2018-09-11
发明人： Xinshu Cai , Shyue Seng Tan , Danny Pak-Chum Shum
IPC分类号： H01L27/11524 , H01L29/788 , G11C11/56 , G11C16/04
摘要： In a non-limiting embodiment, a memory array is provided having a transistor device. The transistor device includes transistor device first, second and third doped regions in a substrate. The transistor device further includes a first transistor device select gate over a region between the transistor device first doped region and the transistor device second doped region, and a second transistor device select gate over a region between the transistor device first doped region and the transistor device third doped region. The transistor device further includes a transistor device dielectric barrier extending between the first transistor device select gate and the second transistor device select gate. A width of the dielectric barrier compared to a width of the first transistor device select gate and/or the second transistor device select gate may have a ratio ranging from 0.33:1 to 5:1.
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公开(公告)号：US10978510B2
公开(公告)日：2021-04-13
申请号：US16443255
申请日：2019-06-17
发明人： Pinghui Li , Haiqing Zhou , Liying Zhang , Wanbing Yi , Ming Zhu , Danny Pak-Chum Shum , Darin Chan
IPC分类号： H01L27/22 , H01L43/02 , H01L43/08 , G11C5/02 , G11C11/16 , H01L27/02 , H01L43/12 , G11C11/15
摘要： Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
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公开(公告)号：US10693054B2
公开(公告)日：2020-06-23
申请号：US16046648
申请日：2018-07-26
发明人： Danny Pak-Chum Shum , Wanbing Yi , Curtis Chun-I Hsieh , Yi Jiang , Juan Boon Tan , Benfu Lin
摘要： A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
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公开(公告)号：US10446607B2
公开(公告)日：2019-10-15
申请号：US15393200
申请日：2016-12-28
发明人： Wanbing Yi , Curtis Chun-I Hsieh , Juan Boon Tan , Soh Yun Siah , Hai Cong , Alex See , Young Seon You , Danny Pak-Chum Shum , Hyunwoo Yang
摘要： Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.
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公开(公告)号：US10411027B2
公开(公告)日：2019-09-10
申请号：US15787764
申请日：2017-10-19
发明人： Ming Zhu , Pinghui Li , Eng Huat Toh , Yiang Aun Nga , Danny Pak-Chum Shum
IPC分类号： H01L29/78 , H01L29/66 , H01L29/792 , H01L27/1157 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L27/11568 , H01L29/423 , H01L27/11573
摘要： Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.
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公开(公告)号：US10374005B2
公开(公告)日：2019-08-06
申请号：US15858655
申请日：2017-12-29
发明人： Pinghui Li , Haiqing Zhou , Liying Zhang , Wanbing Yi , Ming Zhu , Danny Pak-Chum Shum , Darin Chan
摘要： Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
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7.发明授权公开(公告)号：US10361162B1
公开(公告)日：2019-07-23
申请号：US15878139
申请日：2018-01-23
IPC分类号： H01L23/552 , G11C11/16 , H01L27/22 , H01L25/16 , H01L21/78 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/485
摘要： Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
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公开(公告)号：US10312442B2
公开(公告)日：2019-06-04
申请号：US15711370
申请日：2017-09-21
摘要： Non-volatile memory (NVM) devices, resistive random access memory (RRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a non-volatile memory (NVM) device includes a first electrode and a second electrode positioned above the first electrode. Further, the NVM device includes a variable resistance material layer positioned between the first electrode and the second electrode. The variable resistance material layer contains magnesium oxide.
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公开(公告)号：US10290679B1
公开(公告)日：2019-05-14
申请号：US15917084
申请日：2018-03-09
发明人： Bharat Bhushan , Juan Boon Tan , Yi Jiang , Danny Pak-Chum Shum , Wanbing Yi
摘要： A scalable method of forming an integrated high-density STT-MRAM with a 3D array of multi-level MTJs and the resulting devices are provided. Embodiments include providing a Si substrate of an X-density STT-MRAM having an array of interconnect stacks; forming a level of a MTJ structure on each of a first interconnect stack and a second interconnect stack, wherein (X−1) defines a number of interconnect stacks between the first and the second interconnect stacks; forming a via on each interconnect stack without a MTJ structure; forming a metal layer on each MTJ structure and via on the level; repeating the forming of the MTJ structure, the via, and the metal layer one interconnect stack laterally shifted until the level of the MTJ structure equals X, only forming the MTJ structure at that level; forming a bit line over the substrate; and connecting the bit line to each MTJ structure.
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公开(公告)号：US20190123059A1
公开(公告)日：2019-04-25
申请号：US15787764
申请日：2017-10-19
发明人： Ming Zhu , Pinghui Li , Eng Huat Toh , Yiang Aun Nga , Danny Pak-Chum Shum
IPC分类号： H01L27/11568 , H01L27/11573 , H01L29/423 , H01L29/78
CPC分类号： H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L29/42344 , H01L29/7851
摘要： Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.
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