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公开(公告)号：US20110063042A1
公开(公告)日：2011-03-17
申请号：US12952395
申请日：2010-11-23
申请人： Greg Mendolia , James Andrew Martin, III , Izz Khayo , Cornelis Frederik Du Toit , Heinz Bachmann , William McKinzie
发明人： Greg Mendolia , James Andrew Martin, III , Izz Khayo , Cornelis Frederik Du Toit , Heinz Bachmann , William McKinzie
IPC分类号： H03H7/38
摘要： An embodiment of the present invention provides an apparatus, comprising an input port and a dynamic impedance matching network capable of determining a mismatch at the input port and dynamically changing the RF match by using at least one matching element that includes at least one voltage tunable dielectric capacitor. The matching network may be a “Pi”, a “T”, or “ladder” type network and the apparatus may further comprise at least one directional coupler capable of signal collection by sampling a portion of an incident signal, a reflected signal or both. In an embodiment of the present invention, the apparatus may also include a control and power control & logic unit (PC LU) to convert input analog signals into digital signals and sensing VSWR phase and magnitude and processing the digital signals using an algorithm to give it a voltage value and wherein the voltage values may be compared to values coming from the coupler and once compared and matched, the values may be passed to a Hi Voltage Application Specific Integrated Circuit (HV ASIC) to transfer and distribute compensatory voltages to the matching network elements. Additional embodiments are disclosed.
摘要翻译： 本发明的实施例提供了一种装置，其包括输入端口和动态阻抗匹配网络，其能够通过使用至少一个匹配元件来确定输入端口处的失配并动态地改变RF匹配，该匹配元件包括至少一个电压可调电介质 电容器。 匹配网络可以是“Pi”，“T”或“梯形”型网络，并且该装置还可以包括至少一个定向耦合器，其能够通过对入射信号的一部分，反射信号或两者进行采样来进行信号采集 。 在本发明的一个实施例中，该装置还可以包括控制和功率控制与逻辑单元（PC LU），用于将输入的模拟信号转换成数字信号，并且使用算法给VSWR相位和幅度并处理数字信号 电压值，并且其中电压值可以与来自耦合器的值进行比较，并且一旦比较和匹配，则该值可以被传递到高电压专用集成电路（HV ASIC），以将补偿电压传输和分配给匹配网络 元素。 公开了另外的实施例。
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公开(公告)号：US07865154B2
公开(公告)日：2011-01-04
申请号：US11245898
申请日：2005-10-08
申请人： Greg Mendolia , James Andrew Martin, III , Izz Khayo , Cornelis Frederik du Toit , Heinz Bachmann , William McKinzie
发明人： Greg Mendolia , James Andrew Martin, III , Izz Khayo , Cornelis Frederik du Toit , Heinz Bachmann , William McKinzie
IPC分类号： H04B1/04
摘要： An embodiment of the present invention provides an apparatus, comprising an input port and a dynamic impedance matching network capable of determining a mismatch at the input port and dynamically changing the RF match by using at least one matching element that includes at least one voltage tunable dielectric capacitor. The matching network may be a “Pi”, a “T”, or “ladder” type network and the apparatus may further comprise at least one directional coupler capable of signal collection by sampling a portion of an incident signal, a reflected signal or both. In an embodiment of the present invention, the apparatus may also include a control and power control & logic unit (PC LU) to convert input analog signals into digital signals and sensing VSWR phase and magnitude and processing the digital signals using an algorithm to give it a voltage value and wherein the voltage values may be compared to values coming from the coupler and once compared and matched, the values may be passed to a Hi Voltage Application Specific Integrated Circuit (HV ASIC) to transfer and distribute compensatory voltages to the matching network elements.
摘要翻译： 本发明的实施例提供了一种装置，其包括输入端口和动态阻抗匹配网络，其能够通过使用至少一个匹配元件来确定输入端口处的失配并动态地改变RF匹配，该匹配元件包括至少一个电压可调电介质 电容器。 匹配网络可以是“Pi”，“T”或“梯形”型网络，并且该装置还可以包括至少一个定向耦合器，其能够通过对入射信号的一部分，反射信号或两者进行采样来进行信号采集 。 在本发明的一个实施例中，该装置还可以包括控制和功率控制与逻辑单元（PC LU），用于将输入的模拟信号转换成数字信号，并且使用算法给VSWR相位和幅度并处理数字信号 电压值，并且其中电压值可以与来自耦合器的值进行比较，并且一旦比较和匹配，则该值可以被传递到高电压专用集成电路（HV ASIC），以将补偿电压传输和分配给匹配网络 元素。
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公开(公告)号：US08744384B2
公开(公告)日：2014-06-03
申请号：US12952395
申请日：2010-11-23
申请人： Gregory Mendolia , James Andrew Martin, III , Izz Khayo , Cornelis Frederik Du Toit , Heinz Bachmann , William McKinzie
发明人： Gregory Mendolia , James Andrew Martin, III , Izz Khayo , Cornelis Frederik Du Toit , Heinz Bachmann , William McKinzie
IPC分类号： H04B1/04
摘要： An embodiment of the present invention provides an apparatus, comprising an input port and a dynamic impedance matching network capable of determining a mismatch at the input port and dynamically changing the RF match by using at least one matching element that includes at least one voltage tunable dielectric capacitor. The matching network may be a “Pi”, a “T”, or “ladder” type network and the apparatus may further comprise at least one directional coupler capable of signal collection by sampling a portion of an incident signal, a reflected signal or both. In an embodiment of the present invention, the apparatus may also include a control and power control & logic unit (PC LU) to convert input analog signals into digital signals and sensing VSWR phase and magnitude and processing the digital signals using an algorithm to give it a voltage value and wherein the voltage values may be compared to values coming from the coupler and once compared and matched, the values may be passed to a Hi Voltage Application Specific Integrated Circuit (HV ASIC) to transfer and distribute compensatory voltages to the matching network elements. Additional embodiments are disclosed.
摘要翻译： 本发明的实施例提供了一种装置，其包括输入端口和动态阻抗匹配网络，其能够通过使用至少一个匹配元件来确定输入端口处的失配并动态地改变RF匹配，该匹配元件包括至少一个电压可调电介质 电容器。 匹配网络可以是“Pi”，“T”或“梯形”型网络，并且该装置还可以包括至少一个定向耦合器，其能够通过对入射信号的一部分，反射信号或两者进行采样来进行信号采集 。 在本发明的一个实施例中，该装置还可以包括控制和功率控制与逻辑单元（PC LU），用于将输入的模拟信号转换成数字信号，并且使用算法给VSWR相位和幅度并处理数字信号 电压值，并且其中电压值可以与来自耦合器的值进行比较，并且一旦比较和匹配，则该值可以被传递到高电压专用集成电路（HV ASIC），以将补偿电压传输和分配给匹配网络 元素。 公开了另外的实施例。
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公开(公告)号：US20060160501A1
公开(公告)日：2006-07-20
申请号：US11245898
申请日：2005-10-08
申请人： Greg Mendolia , James Martin , Izz Khayo , Cornelis du Toit , Heinz Bachmann , William McKinzie
发明人： Greg Mendolia , James Martin , Izz Khayo , Cornelis du Toit , Heinz Bachmann , William McKinzie
摘要： An embodiment of the present invention provides an apparatus, comprising an input port and a dynamic impedance matching network capable of determining a mismatch at the input port and dynamically changing the RF match by using at least one matching element that includes at least one voltage tunable dielectric capacitor. The matching network may be a “Pi”, a “T”, or “ladder” type network and the apparatus may further comprise at least one directional coupler capable of signal collection by sampling a portion of an incident signal, a reflected signal or both. In an embodiment of the present invention, the apparatus may also include a control and power control & logic unit (PC LU) to convert input analog signals into digital signals and sensing VSWR phase and magnitude and processing the digital signals using an algorithm to give it a voltage value and wherein the voltage values may be compared to values coming from the coupler and once compared and matched, the values may be passed to a Hi Voltage Application Specific Integrated Circuit (HV ASIC) to transfer and distribute compensatory voltages to the matching network elements.
摘要翻译： 本发明的实施例提供了一种装置，其包括输入端口和动态阻抗匹配网络，其能够通过使用至少一个匹配元件来确定输入端口处的失配并动态地改变RF匹配，该匹配元件包括至少一个电压可调电介质 电容器。 匹配网络可以是“Pi”，“T”或“梯形”型网络，并且该装置还可以包括至少一个定向耦合器，其能够通过对入射信号的一部分，反射信号或两者进行采样来进行信号采集 。 在本发明的一个实施例中，该装置还可以包括控制和功率控制与逻辑单元（PC LU），用于将输入的模拟信号转换成数字信号，并且使用算法给VSWR相位和幅度并处理数字信号 电压值，并且其中电压值可以与来自耦合器的值进行比较，并且一旦比较和匹配，则该值可以被传递到高电压专用集成电路（HV ASIC），以将补偿电压传输和分配给匹配网络 元素。
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5.发明申请Optimized circuits for three dimensional packaging and methods of manufacture therefore 有权因此，用于三维包装的优化电路和制造方法公开(公告)号：US20060214165A1
公开(公告)日：2006-09-28
申请号：US11353930
申请日：2006-02-14
申请人： William Macropoulos , Greg Mendolia , James Oakes , Izz Khayo
发明人： William Macropoulos , Greg Mendolia , James Oakes , Izz Khayo
IPC分类号： H01L29/04
CPC分类号： H05K1/024 , H05K1/142 , H05K1/165 , H05K2201/0187 , H05K2201/09972
摘要： An apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a first substrate and a second portion of the integrated circuit is placed on a second substrate stacked adjacent the first substrate and wherein the first portion and the second portion of the integrated circuit are interconnected.
摘要翻译： 一种包括集成电路的装置，其中所述集成电路的第一部分被放置在第一基板上，并且所述集成电路的第二部分被放置在邻近所述第一基板堆叠的第二基板上，并且其中所述第一部分和所述第二部分 的集成电路互连。
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6.发明授权Optimized circuits for three dimensional packaging and methods of manufacture therefore 有权因此，用于三维包装的优化电路和制造方法公开(公告)号：US07471146B2
公开(公告)日：2008-12-30
申请号：US11353930
申请日：2006-02-14
申请人： William Macropoulos , Greg Mendolia , James G. Oakes , Izz Khayo
发明人： William Macropoulos , Greg Mendolia , James G. Oakes , Izz Khayo
CPC分类号： H05K1/024 , H05K1/142 , H05K1/165 , H05K2201/0187 , H05K2201/09972
摘要： An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.
摘要翻译： 本发明的实施例提供了一种包括集成电路的装置，其中集成电路的第一部分被放置在顶层基板上，并且集成电路的第二部分被放置在邻近顶层的堆叠层 衬底，并且其中集成电路的第一部分和第二部分互连; 并且印刷螺旋臂垂直堆叠在顶层基板的顶表面和底表面上，从而形成高Q电感器。
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