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    Guard wafer for semiconductor structure fabrication
    3.
    发明授权
    Guard wafer for semiconductor structure fabrication 有权
    用于半导体结构制造的保护晶片

    公开(公告)号：US07372689B2

    公开(公告)日：2008-05-13

    申请号：US10907508

    申请日：2005-04-04

    申请人： Scott M. Hargash ,  Pavel Smetana

    发明人： Scott M. Hargash ,  Pavel Smetana

    IPC分类号： H02N13/00

    CPC分类号： C23C16/4581 ,  C23C16/4404 ,  H01L21/6831

    摘要： An apparatus (and method for operating the same) which allows tightly coupling the device wafer to the electrostatic chuck of the process chamber after the process chamber is conditioned. The method comprises (a) providing (i) a process chamber and (ii) an electrostatic chuck in the process chamber; (b) placing a guard wafer on the electrostatic chuck via a top surface of the electrostatic chuck; and (c) forming a particle restraining layer on essentially all surfaces that are exposed to the ambient inside the process chamber, wherein the particle restraining layer has a thickness in a first direction of at least 500 Å, wherein the first direction is essentially perpendicular to an interfacing surface between the particle restraining layer and an inner surface of the process chamber, and wherein the guard wafer comprises a material selected from the group consisting of a metal and a semiconductor oxide.

    摘要翻译： 一种用于操作该装置的装置（及其操作方法），其允许在处理室被调节之后将装置晶片紧密地耦合到处理室的静电卡盘。 该方法包括（a）在处理室中提供（i）处理室和（ii）静电卡盘; （b）通过静电卡盘的顶表面将防护晶片放置在静电卡盘上; 并且（c）在基本上暴露于处理室内的环境的所有表面上形成颗粒抑制层，其中所述颗粒限制层具有至少在第一方向上的厚度，其中所述第一方向基本上垂直于 颗粒限制层和处理室的内表面之间的接合表面，并且其中防护晶片包括选自金属和半导体氧化物的材料。

    Guard wafer for semiconductor structure fabrication
    4.
    发明授权
    Guard wafer for semiconductor structure fabrication 有权
    用于半导体结构制造的保护晶片

    公开(公告)号：US07489494B2

    公开(公告)日：2009-02-10

    申请号：US12101231

    申请日：2008-04-11

    申请人： Scott M. Hargash ,  Pavel Smetana

    发明人： Scott M. Hargash ,  Pavel Smetana

    IPC分类号： H02N13/00

    CPC分类号： C23C16/4581 ,  C23C16/4404 ,  H01L21/6831

    摘要： An apparatus which allows tightly coupling of the device wafer to the electrostatic chuck of the process chamber after the process chamber is conditioned. The apparatus includes (a) a process chamber; (b) a chuck in the process chamber; (c) a guard wafer placed on and in direct physical contact with the chuck; and (d) a particle restraining layer on essentially all surfaces that are exposed to the ambient inside the process chamber. The particle restraining layer has a thickness in a first direction of at least 500 nm. The first direction is essentially perpendicular to an interfacing surface between the particle restraining layer and the chuck. The guard wafer comprises a material selected from the group consisting of a metal and a semiconductor oxide.

    摘要翻译： 在处理室被调节之后允许将器件晶片与处理室的静电卡盘紧密耦合的装置。 该装置包括（a）处理室; （b）处理室中的卡盘; （c）放置在与卡盘直接物理接触的保护晶片; 和（d）在基本上所有表面上的暴露于处理室内的环境的颗粒抑制层。 粒子限制层的厚度在第一方向上至少为500nm。 第一方向基本上垂直于颗粒限制层和卡盘之间的界面表面。 保护晶片包括选自金属和半导体氧化物的材料。

    GUARD WAFER FOR SEMICONDUCTOR STRUCTURE FABRICATION
    5.
    发明申请
    GUARD WAFER FOR SEMICONDUCTOR STRUCTURE FABRICATION 有权
    用于半导体结构制造的保护膜

    公开(公告)号：US20080210161A1

    公开(公告)日：2008-09-04

    申请号：US12101231

    申请日：2008-04-11

    申请人： Scott M. Hargash ,  Pavel Smetana

    发明人： Scott M. Hargash ,  Pavel Smetana

    IPC分类号： B05C13/02

    CPC分类号： C23C16/4581 ,  C23C16/4404 ,  H01L21/6831

    摘要： An apparatus which allows tightly coupling of the device wafer to the electrostatic chuck of the process chamber after the process chamber is conditioned. The apparatus includes (a) a process chamber; (b) a chuck in the process chamber; (c) a guard wafer placed on and in direct physical contact with the chuck; and (d) a particle restraining layer on essentially all surfaces that are exposed to the ambient inside the process chamber. The particle restraining layer has a thickness in a first direction of at least 500 nm. The first direction is essentially perpendicular to an interfacing surface between the particle restraining layer and the chuck. The guard wafer comprises a material selected from the group consisting of a metal and a semiconductor oxide.

    摘要翻译： 在处理室被调节之后允许将器件晶片与处理室的静电卡盘紧密耦合的装置。 该装置包括（a）处理室; （b）处理室中的卡盘; （c）放置在与卡盘直接物理接触的保护晶片; 和（d）在基本上所有表面上的暴露于处理室内的环境的颗粒抑制层。 粒子限制层的厚度在第一方向上至少为500nm。 第一方向基本上垂直于颗粒限制层和卡盘之间的界面表面。 保护晶片包括选自金属和半导体氧化物的材料。