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公开(公告)号：US08726113B2
公开(公告)日：2014-05-13
申请号：US13453929
申请日：2012-04-23
IPC分类号： G01R31/28
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译： 用于处理未知状态问题的集成电路的内置自检技术。 一些实现使用与时间压缩器相连的专用扫描链选择器。 专门的扫描链选择器的存在提高了掩蔽X状态的效率。 还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3） 以处理过度掩蔽现象。
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2.发明授权Compression based on deterministic vector clustering of incompatible test cubes 有权基于不兼容测试立方体的确定性向量聚类的压缩公开(公告)号：US08347159B2
公开(公告)日：2013-01-01
申请号：US12718813
申请日：2010-03-05
IPC分类号： G06F11/00
CPC分类号： G01R31/31921 , G01R31/318547
摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.
摘要翻译： 测试数据压缩方案基于确定性向量聚类。 在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。 父模式以及表示冲突位的控制模式和增量模式被有效地编码。 三模式解压缩器可用于解压缩测试数据。
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公开(公告)号：US20120210181A1
公开(公告)日：2012-08-16
申请号：US13453929
申请日：2012-04-23
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译： 用于处理未知状态问题的集成电路的内置自检技术。 一些实现使用与时间压缩器相连的专用扫描链选择器。 专门的扫描链选择器的存在提高了掩蔽X状态的效率。 还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3） 以处理过度掩蔽现象。
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公开(公告)号：US08166359B2
公开(公告)日：2012-04-24
申请号：US12341996
申请日：2008-12-22
IPC分类号： G01R31/28
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
摘要翻译： 用于处理未知状态问题的集成电路的内置自检技术。 一些实现使用与时间压缩器相连的专用扫描链选择器。 专门的扫描链选择器的存在提高了掩蔽X状态的效率。 还公开了：（1）与多个扫描链和时间压实器一起工作的选择器的架构，（2）用于确定和编码随后抑制X状态的每个周期扫描链选择掩模的方法，以及（3） 以处理过度掩蔽现象。
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公开(公告)号：US08832512B2
公开(公告)日：2014-09-09
申请号：US13049829
申请日：2011-03-16
申请人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： Dariusz Czysz , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
IPC分类号： G06F11/00
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译： 公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。 所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。 可以通过产生低切换控制模式来进一步降低功耗。
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公开(公告)号：US20110231721A1
公开(公告)日：2011-09-22
申请号：US13049829
申请日：2011-03-16
申请人： DARIUSZ CZYSZ , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
发明人： DARIUSZ CZYSZ , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Przemyslaw Szczerbicki , Jerzy Tyszer
CPC分类号： G06F11/079
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.
摘要翻译： 公开了涉及用于具有冲突的测试立方体的确定性聚类的功率感知测试应用的方法，装置和系统的代表性实施例。 所公开的技术的实施例可以用于产生低切换父模式，以降低测试集成电路期间的功耗。 可以通过产生低切换控制模式来进一步降低功耗。
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7.发明申请Compression Based On Deterministic Vector Clustering Of Incompatible Test Cubes 有权基于不相容性测试立方体的确定性矢量聚类的压缩公开(公告)号：US20100229060A1
公开(公告)日：2010-09-09
申请号：US12718813
申请日：2010-03-05
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31921 , G01R31/318547
摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.
摘要翻译： 测试数据压缩方案基于确定性向量聚类。 在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。 父模式以及表示冲突位的控制模式和增量模式被有效地编码。 三模式解压缩器可用于解压缩测试数据。
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公开(公告)号：US20180143249A1
公开(公告)日：2018-05-24
申请号：US15875589
申请日：2018-01-19
IPC分类号： G01R31/317 , G06F11/27 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/31703 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318547 , G06F11/27
摘要： Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
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公开(公告)号：US09088522B2
公开(公告)日：2015-07-21
申请号：US13980287
申请日：2012-01-17
申请人： Janusz Rajski , Mark A Kassab , Grzegorz Mrugalski , Nilanjan Mukherjee , Jakub Janicki , Jerzy Tyszer , Avijit Dutta
发明人： Janusz Rajski , Mark A Kassab , Grzegorz Mrugalski , Nilanjan Mukherjee , Jakub Janicki , Jerzy Tyszer , Avijit Dutta
IPC分类号： H04L12/26 , G01R31/3183 , G06F11/263
CPC分类号： H04L43/50 , G01R31/318335 , G06F11/263
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.
摘要翻译： 公开了用于在电路系统中测试多个核的测试调度的方法，装置和系统的代表性实施例。 编码测试数据以导出需要少量核心输入通道的压缩测试模式。 相应地确定每个压缩测试图案的核心输入/输出通道要求信息。 压缩的模式被分组成测试模式类。 测试模式类的形成之后是分配电路输入和输出通道以及测试应用时隙，其可以包括将互补测试模式类合并成可以与特定测试访问机制一起工作的集群。 可以独立于测试数据设计测试访问机制。
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公开(公告)号：US10955460B2
公开(公告)日：2021-03-23
申请号：US13635683
申请日：2011-03-16
申请人： Mark Kassab , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Jakub Janicki , Jerzy Tyszer
发明人： Mark Kassab , Grzegorz Mrugalski , Nilanjan Mukherjee , Janusz Rajski , Jakub Janicki , Jerzy Tyszer
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3185 , G01R31/3183
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
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