公开(公告)号：US20100281231A1

公开(公告)日：2010-11-04

申请号：US12431874

申请日：2009-04-29

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F12/00 ,  G06F9/46

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流至少部分地基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US20120331226A1

公开(公告)日：2012-12-27

申请号：US13600614

申请日：2012-08-31

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F12/08

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US08645639B2

公开(公告)日：2014-02-04

申请号：US13600614

申请日：2012-08-31

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F13/18

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US08266389B2

公开(公告)日：2012-09-11

申请号：US12431874

申请日：2009-04-29

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F13/18

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流至少部分地基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US07519755B2

公开(公告)日：2009-04-14

申请号：US10964884

申请日：2004-10-14

申请人： Thomas Kunjan ,  Joerg Winkler ,  Frank Barth

发明人： Thomas Kunjan ,  Joerg Winkler ,  Frank Barth

IPC分类号： G06F13/00

CPC分类号： G06F13/4273

摘要： An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

摘要翻译： 提供具有第一和第二电路单元的集成电路芯片，特别是南桥。 每个电路单元可以向另一个电路单元发送请求，并在接收到需要响应的请求时发送响应。 第一电路单元连接到第二电路单元，以向第二电路单元发送与由第一电路单元发送的请求相关的数据，以及与第一电路单元通过共享的要发送的响应有关的响应数据 信号线。

公开(公告)号：US20060047877A1

公开(公告)日：2006-03-02

申请号：US11011511

申请日：2004-12-14

申请人： Joerg Winkler ,  Frank Barth

发明人： Joerg Winkler ,  Frank Barth

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.

摘要翻译： 提供一种中断处理技术，其中响应于来自单个设备的中断请求将中断消息发送到处理器的中断控制器。 中断消息包括存储器地址和中断状态信息。 存储器地址被专门分配给发出中断请求的设备。 中断状态信息表示设备的中断状态。 存储在存储器中的中断表由中断控制器使用中断消息中包含的中断状态信息进行更新。 中断表保存设备特定的中断状态。 更新中断表包括使用中断消息中的存储器地址寻址存储器。

公开(公告)号：US07016994B2

公开(公告)日：2006-03-21

申请号：US10285935

申请日：2002-11-01

申请人： Joerg Winkler ,  Frank Barth

发明人： Joerg Winkler ,  Frank Barth

IPC分类号： G06F13/14

CPC分类号： G06F13/36

摘要： An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective requestor. The requests are placed by the respective requestor by asserting a request signal, and the request signal is deasserted by the respective requestor when a response is sent back. A retry request may be sent to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later. Together with the retry request, a ready signal is sent indicating whether the request could be processed. This allows the requestor to modify its request when retrying it, if the request was not yet processed.

摘要翻译： 提供了可以应用于连接到南桥的PCI（外围组件互连）设备的改进的接口技术。 从至少一个请求者收到请求。 请求需要将响应发回给相应的请求者。 请求由相应的请求者通过断言请求信号来放置，并且当发送回应时，请求信号由相应的请求者解除断言。 可以向当前请求者发送重试请求，以请求当前请求者解除其请求信号，尽管响应尚未被发送回来，并且稍后重新发送请求信号。 与重试请求一起发送就绪信号，指示是否可以处理该请求。 这允许请求者在重试时修改其请求，如果请求尚未处理。

公开(公告)号：US06671748B1

公开(公告)日：2003-12-30

申请号：US09904374

申请日：2001-07-11

申请人： Terry Lynn Cole ,  Dale E. Gulick ,  Timothy C. Maleck ,  Frank Barth ,  Joerg Winkler

发明人： Terry Lynn Cole ,  Dale E. Gulick ,  Timothy C. Maleck ,  Frank Barth ,  Joerg Winkler

IPC分类号： G06F1300

CPC分类号： G06F13/387

摘要： A method and apparatus for passing device configuration information to a shared controller. In one embodiment, a host controller may be configured to read configuration from one or more peripheral devices coupled to a serial bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device. Additional information needed to configure the device to communicate over the peripheral bus may also be obtained with a read of the device, or various lookup mechanisms, such as a lookup table or a tree-like data structure. After configuration information has been obtained for each device coupled to the bus, the host controller may dynamically configure each of the devices for communication over the bus, thereby allowing the flexibility to enumerate riser cards and add new functions through peripheral devices to the computer system in which the bus is implemented.

摘要翻译： 一种用于将设备配置信息传递到共享控制器的方法和装置。 在一个实施例中，主机控制器可以被配置为从耦合到串行总线的一个或多个外围设备读取配置。 外围设备可以包括编码器/解码器（编解码器）电路，并且可以使用转接卡来实现。 主机控制器可以采用几种不同技术中的一种或多种，​​以便从外围设备读取配置信息。 配置信息至少包括设备标识符，其可以标识供应商和设备的功能。 通过设备的读取或诸如查找表或树状数据结构的各种查找机制也可以获得将设备配置成通过外围总线进行通信所需的附加信息。 在针对耦合到总线的每个设备获得配置信息之后，主机控制器可以动态地配置每个设备以通过总线进行通信，从而允许灵活地枚举转接卡并且通过外围设备将新功能添加到计算机系统 总线实施。

公开(公告)号：US08244950B2

公开(公告)日：2012-08-14

申请号：US10285931

申请日：2002-11-01

申请人： Frank Barth ,  Larry Hewitt ,  Joerg Winkler ,  Paul Miranda

发明人： Frank Barth ,  Larry Hewitt ,  Joerg Winkler ,  Paul Miranda

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F13/36

CPC分类号： G06F13/4059

摘要： An improved interface technique for use in a southbridge or I/O hub or in similar devices is provided where non-posted read requests are received from at least one requestor, and upstream commands based on these requests are transmitted. Response data is received in reply to commands that were previously transmitted, and responses are transmitted to the at least one requester based on the response data. A buffer unit is provided for storing command identification data that identifies commands that were already transmitted or that are still to be transmitted, and response availability data that specifies response data that has been received by the receive engine. The improvement may enable multiple outstanding read requests.

摘要翻译： 提供了一种在南桥或I / O集线器或类似设备中使用的改进的接口技术，其中从至少一个请求者接收非发布的读取请求，并且发送基于这些请求的上行命令。 接收响应数据以回复先前发送的命令，并且响应基于响应数据被发送到至少一个请求者。 提供缓冲单元，用于存储识别已发送或尚待发送的命令的命令识别数据，以及指定已被接收引擎接收到的响应数据的响应可用性数据。 改进可能会使多个未完成的读取请求。

公开(公告)号：US07257658B2

公开(公告)日：2007-08-14

申请号：US11011511

申请日：2004-12-14

申请人： Joerg Winkler ,  Frank Barth

发明人： Joerg Winkler ,  Frank Barth

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.

摘要翻译： 提供一种中断处理技术，其中响应于来自单个设备的中断请求将中断消息发送到处理器的中断控制器。 中断消息包括存储器地址和中断状态信息。 存储器地址被专门分配给发出中断请求的设备。 中断状态信息表示设备的中断状态。 存储在存储器中的中断表由中断控制器使用中断消息中包含的中断状态信息进行更新。 中断表保存设备特定的中断状态。 更新中断表包括使用中断消息中的存储器地址寻址存储器。