公开(公告)号：US08853764B1

公开(公告)日：2014-10-07

申请号：US13832682

申请日：2013-03-15

申请人： Guowei Zhang ,  Deyan Chen

发明人： Guowei Zhang ,  Deyan Chen

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7817 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A method for forming a low Rdson LDNMOS and a high sheet resistance poly resistor and the resulting device are provided. Embodiments include forming first, second, and third STI regions in a substrate; forming a P-well in the substrate around the first STI region with a first mask; forming an N-drift region in the substrate between the P-well and the third STI region with the first mask; forming a dielectric layer over the substrate; forming a poly-silicon layer over the dielectric layer; performing an N-drain implant between the second and third STI regions with a second mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the second mask; and patterning the poly-silicon and dielectric layers subsequent to performing the resistance adjustment implant to form a gate stack and a poly resistor, the poly resistor being formed over the third STI region and laterally separated from the gate stack.

摘要翻译： 提供了用于形成低Rdson LDNMOS和高电阻聚电阻器的方法以及所得到的器件。 实施例包括在衬底中形成第一，第二和第三STI区域; 用第一掩模在第一STI区周围的衬底中形成P阱; 在具有第一掩模的P阱和第三STI区之间的衬底中形成N漂移区; 在所述衬底上形成介电层; 在所述电介质层上形成多晶硅层; 在第二和第三STI区域之间用第二掩模执行N-漏极注入; 在所述第二掩模中对所述多晶硅层进行电阻调整注入，但不通过所述多晶硅层; 以及在执行所述电阻调节注入之后构图所述多晶硅和电介质层以形成栅极堆叠和多晶硅电阻器，所述多晶硅电阻器形成在所述第三STI区域上并且与所述栅极叠层横向分离。

公开(公告)号：US08802484B1

公开(公告)日：2014-08-12

申请号：US13747009

申请日：2013-01-22

申请人： Purakh Raj Verma ,  Guowei Zhang ,  Kah Wee Ang

发明人： Purakh Raj Verma ,  Guowei Zhang ,  Kah Wee Ang

IPC分类号： H01L21/00 ,  H01L31/102

CPC分类号： H01L21/02532 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/1203 ,  H01L31/028

摘要： A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.

摘要翻译： 提供了一种通过Ge或Ge / Si的非选择性外延生长在CMOS工艺中形成集成的Ge或Ge / Si光电检测器的方法和装置。 实施例包括在Si衬底中形成N阱; 在Si衬底中形成晶体管或电阻器; 在Si衬底和晶体管或电阻器上形成ILD; 在ILD上形成Si基电介质层; 在所述Si基电介质层上形成多晶硅或Si-Si层; 在多晶硅或a-Si层中形成沟槽，Si基介电层，ILD和N阱; 在沟槽中形成Ge或Ge / Si; 并且将Ge或Ge / Si，多晶硅或a-Si层以及Si基介电层除去到ILD的上表面。 另外的方面包括在Ge或Ge / Si上形成原位掺杂的Si帽外延层或非原位掺杂的多晶Si或者a-Si覆盖层。

公开(公告)号：US08507983B2

公开(公告)日：2013-08-13

申请号：US13550571

申请日：2012-07-16

申请人： Guowei Zhang ,  Purakh Raj Verma

发明人： Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included.

摘要翻译： 公开了一种设备。 该器件包括用有源器件区域制备的衬底。 有源器件区域包括栅极。 该器件还包括在栅极的第一边缘附近设置在衬底中的掺杂沟道。 栅极的第一边缘与沟道的沟道边缘很好地与沟道的沟道边缘重叠。 栅极和沟道边缘的第一个边缘定义了器件的有效沟道长度。 有效通道长度与栅极自对准。 还包括与栅极的第二边缘相邻的掺杂漂移阱。

公开(公告)号：US08222130B2

公开(公告)日：2012-07-17

申请号：US12500620

申请日：2009-07-10

申请人： Guowei Zhang ,  Purakh Raj Verma

发明人： Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L21/22

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of forming a device is presented. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is provided on the substrate corresponding to the gate. The substrate is patterned to at least remove portions of a top gate stack layer unprotected by the first mask. A second mask is also provided on the substrate with an opening exposing a portion of the first mask and the top gate stack layer. A channel well is formed by implanting ions through the opening and gate stack layers into the substrate.

摘要翻译： 提出了一种形成装置的方法。 该方法包括提供用活性器件区域制备的衬底。 有源器件区域包括至少包括栅极电介质层上的栅极电极层的栅极堆叠的栅极堆叠层。 在对应于栅极的基板上设置第一掩模。 将衬底图案化以至少去除未被第一掩模保护的顶部栅极堆叠层的部分。 在基板上还设有第二掩模，该开口具有暴露第一掩模和顶栅层叠层的一部分的开口。 通过将离子通过开口和栅极堆叠层注入衬底而形成通道阱。

公开(公告)号：US07570737B2

公开(公告)日：2009-08-04

申请号：US11801279

申请日：2007-05-08

申请人： Kejun Kang ,  Li Zhang ,  Zhiqiang Chen ,  Haifeng Hu ,  Yuanjing Li ,  Yinong Liu ,  Guowei Zhang ,  Ziran Zhao ,  Yuxiang Xing ,  Yongshun Xiao

发明人： Kejun Kang ,  Li Zhang ,  Zhiqiang Chen ,  Haifeng Hu ,  Yuanjing Li ,  Yinong Liu ,  Guowei Zhang ,  Ziran Zhao ,  Yuxiang Xing ,  Yongshun Xiao

IPC分类号： G01N23/04

CPC分类号： G01N23/046 ,  A61B6/027 ,  G01N2223/419 ,  G06T7/0008 ,  G06T7/97 ,  G06T2207/10081 ,  G06T2207/20016 ,  G06T2207/30112 ,  Y10S378/901

摘要： A cargo security inspection method and system based on spiral scanning, the method including: spirally scanning an inspected object at a first precision to obtain the transmission projection data; judging whether there is a suspect area in the inspected area; scanning at least one slice of the suspect area at a second precision wherein the second precision is greater than the first precision; reconstructing a tomographic image of the at least one slice; and using the reconstructed tomographic image to judge whether there is any dangerous article in the suspect area.

摘要翻译： 一种基于螺旋扫描的货物安全检查方法和系统，所述方法包括：以第一精度螺旋扫描检查对象以获得传输投影数据; 判断被检区域是否有可疑区域; 以第二精度扫描所述可疑区域的至少一个切片，其中所述第二精度大于所述第一精度; 重建所述至少一个切片的断层图像; 并使用重建的断层图像来判断可疑区域中是否存在任何危险物品。

公开(公告)号：US08809150B2

公开(公告)日：2014-08-19

申请号：US13587059

申请日：2012-08-16

申请人： Guowei Zhang ,  Purakh Raj Verma ,  Zhiqing Li

发明人： Guowei Zhang ,  Purakh Raj Verma ,  Zhiqing Li

IPC分类号： H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7835

摘要： LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.

摘要翻译： 在具有减小厚度的多晶硅层和源极/漏极结的器件中，LDD区域具有高的注入能量。 实施例包括在衬底表面上形成氧化物层，在氧化物层上形成多晶硅层，通过氧化物层和多晶硅层并在衬底表面之下形成第一和第二沟槽，在衬底表面之下限定栅极区域，注入掺杂剂 在通过第一和第二沟槽的LDD区域中，在栅极区域的相对侧表面上形成间隔物并且延伸到第一和第二沟槽中，并且在第一和第二沟槽中的每一个下方的源极/漏极区域中注入掺杂剂。

公开(公告)号：US08334567B2

公开(公告)日：2012-12-18

申请号：US12916653

申请日：2010-11-01

申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.

摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力。

公开(公告)号：US07824968B2

公开(公告)日：2010-11-02

申请号：US11488117

申请日：2006-07-17

申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L21/332 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.

摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力。

公开(公告)号：US20080014690A1

公开(公告)日：2008-01-17

申请号：US11488117

申请日：2006-07-17

申请人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

发明人： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Purakh Raj Verma

IPC分类号： H01L21/8234

CPC分类号： H01L29/7835 ,  H01L29/404 ,  H01L29/456 ,  H01L29/49 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7846

摘要： First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region

摘要翻译： 第一示例实施例包括在由沟道和第一，第二和第三结区域构成的MOS晶体管（例如LDMOS Tx）上形成应力层。 应力层在通道和Tx的第二结区产生应力。 第二示例性实施例包括在衬底上形成MOS FET和至少一个虚拟栅极。 MOS由栅极，沟道，源极，漏极和漏极漏极组成。 至少一个虚拟栅极位于偏置漏极之上。 在MOS和虚拟栅极上形成应力层。 应力层和虚拟栅极改善了通道和偏移漏极区域的应力

公开(公告)号：US20060134882A1

公开(公告)日：2006-06-22

申请号：US11021030

申请日：2004-12-22

申请人： Guowei Zhang

发明人： Guowei Zhang

IPC分类号： H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/26506 ,  H01L21/76235

摘要： A method of forming a shallow trench isolation (STI) structure wherein the depth of the STI structure has been extended via formation of an underlying silicon oxide region, has been developed. After definition of a shallow trench isolation shape in a top portion of a semiconductor substrate a self-aligned ion implantation procedure is employed to place oxygen ions in portions of the semiconductor substrate exposed at the bottom portion of the shallow trench shape. Growth of a liner layer on the exposed surfaces of the shallow trench shape, or growth of a liner layer followed by anneal procedure, results in activation of the implanted oxygen ions creating the desired silicon oxide region in a portion of the semiconductor substrate underlying the bottom of the shallow trench shape. Insulator filling of the shallow trench shape now results in a deeper STI structure comprised of the insulator filled shallow trench shape and the underlying silicon oxide region.

摘要翻译： 已经开发出形成浅沟槽隔离（STI）结构的方法，其中通过形成下面的氧化硅区域已经延伸了STI结构的深度。 在半导体衬底的顶部部分中定义浅沟槽隔离形状之后，采用自对准离子注入程序将氧离子放置在浅沟槽形状底部暴露的部分半导体衬底中。 在浅沟槽形状的暴露表面上的衬垫层的生长或者衬底层的生长随后退火过程导致注入的氧离子的活化，在半导体衬底底部的一部分中产生所需的氧化硅区域 的浅沟槽形状。 浅沟槽形状的绝缘体填充现在形成了由绝缘体填充的浅沟槽形状和下面的氧化硅区域组成的更深的STI结构。