公开(公告)号：US09574290B2

公开(公告)日：2017-02-21

申请号：US12945501

申请日：2010-11-12

Applicant: David A. Roberts ,  Hao-Yu Lin ,  Thomas R. Bengtson ,  Thomas Rueckes ,  Karl Robinson ,  H. Montgomery Manning ,  Rahul Sen ,  Michel Pires Monteiro

Inventor： David A. Roberts ,  Hao-Yu Lin ,  Thomas R. Bengtson ,  Thomas Rueckes ,  Karl Robinson ,  H. Montgomery Manning ,  Rahul Sen ,  Michel Pires Monteiro

IPC: B05D3/12 ,  D04H1/4382 ,  B05D3/00 ,  C01B31/02 ,  B82Y40/00 ,  B82Y30/00

CPC classification number: D04H1/4382 ,  B05D3/007 ,  B05D3/12 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/168

Abstract: A method for arranging nanotube elements within nanotube fabric layers and films is disclosed. A directional force is applied over a nanotube fabric layer to render the fabric layer into an ordered network of nanotube elements. That is, a network of nanotube elements drawn together along their sidewalls and substantially oriented in a uniform direction. In some embodiments this directional force is applied by rolling a cylindrical element over the fabric layer. In other embodiments this directional force is applied by passing a rubbing material over the surface of a nanotube fabric layer. In other embodiments this directional force is applied by running a polishing material over the nanotube fabric layer for a predetermined time. Exemplary rolling, rubbing, and polishing apparatuses are also disclosed.

Abstract translation: 公开了一种在纳米管织物层和膜内布置纳米管元件的方法。 在纳米管织物层上施加定向力以使织物层成为纳米管元件的有序网络。 也就是说，一个纳米管元件的网络沿其侧壁一起拉伸并且基本上沿均匀的方向取向。 在一些实施例中，通过将圆柱形元件滚动在织物层上而施加该定向力。 在其它实施例中，通过将摩擦材料通过纳米管织物层的表面来施加该定向力。 在其他实施例中，通过在纳米管织物层上运行抛光材料预定时间来施加该定向力。 还公开了示例性的滚动，摩擦和抛光装置。

公开(公告)号：US08895950B2

公开(公告)日：2014-11-25

申请号：US14020095

申请日：2013-09-06

Applicant: Thomas Rueckes ,  H. Montgomery Manning ,  Rahul Sen

Inventor： Thomas Rueckes ,  H. Montgomery Manning ,  Rahul Sen

IPC: H01L29/04 ,  H01L47/00 ,  H01L29/00 ,  H01L29/16

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02203 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/02628 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/1029 ,  H01L29/1606 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1608 ,  H01L51/0003 ,  H01L51/0007 ,  H01L51/0591 ,  H01L51/107 ,  Y10S977/842

Abstract: Methods for passivating a carbonic nanolayer (that is, material layers comprised of low dimensional carbon structures with delocalized electrons such as carbon nanotubes and nanoscopic graphene flecks) to prevent or otherwise limit the encroachment of another material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous carbonic nanolayer to fill in the voids within the porous carbonic nanolayer while one or more other material layers are applied over or alongside the carbonic nanolayer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the carbonic nanolayer) is used to form a barrier layer within a carbonic nanolayer. In other embodiments, carbon structures are combined with and nanoscopic particles to limit the porosity of a carbonic nanolayer.

Abstract translation: 公开了用于钝化碳纳米层的方法（即，由具有离域电子的低维碳结构（例如碳纳米管和纳米级石墨烯斑点）构成的材料层）以防止或以其他方式限制另一材料层的侵入。 在一些实施方案中，将牺牲材料注入多孔碳纳米层​​内以填充多孔碳纳米层​​内的空隙，同时将一种或多种其它材料层涂覆在碳纳米层上或旁边。 一旦其它材料层就位，则去除牺牲材料。 在其它实施方案中，使用非牺牲填料（以不损害碳纳米层的切换功能的方式选择和沉积）在碳纳米层内形成阻挡层。 在其它实施方案中，碳结构与纳米级颗粒结合以限制碳纳米层的孔隙率。

公开(公告)号：US08883575B2

公开(公告)日：2014-11-11

申请号：US13440383

申请日：2012-04-05

Applicant: Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

Inventor： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

IPC: H01L21/336 ,  H01L21/467 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7853 ,  Y10S438/947

Abstract: A process may include forming a mask directly on and above a region selected as an initial semiconductor fin on a substrate and reducing the initial semiconductor fin forming a semiconductor fin that is laterally thinned from the initial semiconductor fin. The process may be carried out causing the mask to recede to a greater degree in the lateral direction than the vertical direction. In various embodiments, the process may include removing material from the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded mask. Electronic devices may include the thinned semiconductor fin as part of a semiconductor device.

Abstract translation: 工艺可以包括在衬底上直接在选择为初始半导体鳍片的区域之上和之上形成掩模，并且减少形成从初始半导体鳍片横向变薄的半导体鳍片的初始半导体鳍片。 可以进行该处理，使得掩模在横向上比垂直方向更大程度地退回。 在各种实施例中，该方法可以包括从散热片半导体去除材料以实现已经在横向退绕的掩模的阴影之下的减薄的半导体鳍片。 电子器件可以包括作为半导体器件的一部分的变薄的半导体鳍片。

公开(公告)号：US08664742B2

公开(公告)日：2014-03-04

申请号：US12622939

申请日：2009-11-20

Applicant: David H. Wells ,  H. Montgomery Manning

Inventor： David H. Wells ,  H. Montgomery Manning

IPC: H01L21/70

CPC classification number: H01L21/3065 ,  H01L21/76232 ,  H01L21/76283

Abstract: An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.

Abstract translation: 公开了一种中间半导体结构，其包括衬底和形成在衬底中的至少一个底切结构。 底切特征可以包括其中具有侧向空腔的垂直开口，垂直开口延伸到横向空腔下方。 横向空腔可以包括刻面侧壁。

公开(公告)号：US08450829B2

公开(公告)日：2013-05-28

申请号：US13198581

申请日：2011-08-04

Applicant: Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

Inventor： Mark Fischer ,  Stephen Russell ,  H. Montgomery Manning

IPC: H01L21/70

CPC classification number: H01L29/06 ,  H01L21/0338 ,  H01L21/3088

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.

Abstract translation: 通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。 通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。 将图案转移到无定形碳层。 侧壁间隔物形成在图案化无定形碳层的侧壁上。 沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。 除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。 去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。 将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

公开(公告)号：US08377819B2

公开(公告)日：2013-02-19

申请号：US13237126

申请日：2011-09-20

Applicant: James Mathew ,  H. Montgomery Manning

Inventor： James Mathew ,  H. Montgomery Manning

IPC: H01L21/4763

CPC classification number: H01L21/76804 ,  H01L21/76801 ,  H01L21/76831 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10888

Abstract: The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes forming a filler material in the trench and removing the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes forming a spacer material on at least one side surface of the trench to the particular depth of the filler material and forming a conductive material in the trench over the filler material.

Abstract translation: 本公开包括各种接触实施方式。 一种这样的方法实施例包括在特定厚度的绝缘体堆叠材料中形成沟槽。 该方法包括在沟槽中形成填充材料，并将填料材料移除到小于绝缘体堆叠材料的特定厚度的特定深度。 该方法还包括在沟槽的至少一个侧表面上形成隔离材料至填充材料的特定深度，并在填充材料上的沟槽中形成导电材料。

公开(公告)号：US08164132B2

公开(公告)日：2012-04-24

申请号：US13073490

申请日：2011-03-28

Applicant: H. Montgomery Manning

Inventor： H. Montgomery Manning

IPC: H01L27/108

CPC classification number: H01L28/91 ,  H01L27/0207 ,  H01L27/10817 ,  H01L27/10852

Abstract: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.

Abstract translation: 本发明包括形成半导体结构的方法和形成多个电容器器件的方法。 本发明的示例性方法包括在绝缘材料的开口内形成导电材料以形成电容器电极结构。 形成与至少一些电极结构物理接触的晶格，在晶格上形成保护帽，随后去除一些绝缘材料以暴露电极结构的外表面。 晶格可以减轻电极结构的结构完整性的倾倒或其它损失，并且保护帽可以保护绝缘材料的被覆盖部分免受蚀刻。 在电极结构的外侧壁露出之后，去除保护盖。 然后将电极结构并入电容器结构。

公开(公告)号：US20120070955A1

公开(公告)日：2012-03-22

申请号：US13302231

申请日：2011-11-22

Applicant: Cem Basceri ,  Gurtej S. Sandhu ,  H. Montgomery Manning

Inventor： Cem Basceri ,  Gurtej S. Sandhu ,  H. Montgomery Manning

IPC: H01L21/02

CPC classification number: H01L21/76823 ,  H01L21/28512 ,  H01L21/76895 ,  Y10T428/12542

Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。 在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。 至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。 接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。 考虑了其他方面和实现。

公开(公告)号：US20110156009A1

公开(公告)日：2011-06-30

申请号：US12651288

申请日：2009-12-31

Applicant: H. Montgomery Manning ,  Thomas Rueckes ,  Claude L. Bertin

Inventor： H. Montgomery Manning ,  Thomas Rueckes ,  Claude L. Bertin

IPC: H01L51/10 ,  H01L51/40

CPC classification number: B82Y10/00 ,  G11C13/025 ,  H01L27/24 ,  H01L29/0665 ,  H01L29/43 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/936

Abstract: An electrical device includes a substrate; first and second active areas; first and second word lines disposed in a first plane; first and second bit lines in a second plane and in electrical communication with first and second active areas; and a reference line disposed in a third plane. A nanotube element disposed in a fourth plane is in electrical communication with first and second active areas and the reference line via electrical connections at a first surface of the nanotube element. The nanotube element includes first and second regions having resistance states that are independently adjustable in response to electrical stimuli, wherein the first and second regions nonvolatilely retain the resistance states. Arrays of such electrical devices can be formed as nonvolatile memory devices. Methods for fabricating such devices are also disclosed.

Abstract translation: 电气装置包括基板; 第一和第二活跃区域; 布置在第一平面中的第一和第二字线; 第一和第二位线在第二平面中并且与第一和第二有效区域电连通; 以及设置在第三平面中的参考线。 设置在第四平面中的纳米管元件通过在纳米管元件的第一表面处的电连接与第一和第二有源区域和参考线路电连通。 纳米管元件包括具有响应于电刺激可独立调节的电阻状态的第一和第二区域，其中第一和第二区域非常地保持电阻状态。 这种电气装置的阵列可以形成为非易失性存储装置。 还公开了制造这种装置的方法。

公开(公告)号：US20110121392A1

公开(公告)日：2011-05-26

申请号：US13017854

申请日：2011-01-31

Applicant: Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

Inventor： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

IPC: H01L27/12

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7853 ,  Y10S438/947

Abstract: A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.

Abstract translation: 工艺可以包括首先通过与散热片半导体的侧壁邻接的电介质硬掩模蚀刻沟槽隔离电介质。 可以执行第一蚀刻以暴露侧壁的至少一部分，使得电介质硬掩模在横向方向上比垂直方向更大程度地退回。 该方法可以包括第二蚀刻鳍式半导体以实现减薄的半导体鳍片，其已经在横向后退的硬掩模的阴影之下后退。 减薄的半导体鳍片可以具有可超过光刻极限的特征尺寸。 电子器件可以包括作为场效应晶体管的一部分的变薄的半导体鳍片。