公开(公告)号：US10482013B2

公开(公告)日：2019-11-19

申请号：US15513407

申请日：2014-09-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Charles S. Johnson ,  Harumi Kuno ,  Goetz Graefe ,  Haris Volos ,  Mark Lillibridge ,  James Hyungsun Park ,  Wey Guy

IPC: G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F11/14

Abstract: Systems and methods associated with page modification are disclosed. One example method may be embodied on a non-transitory computer-readable medium storing computer-executable instructions. The instructions, when executed by a computer, may cause the computer to fetch a page to a buffer pool in a memory. The page may be fetched from at least one of a log and a backup using single page recovery. The instructions may also cause the computer to store a modification of the page to the log. The modification may be stored to the log as a log entry. The instructions may also cause the computer to evict the page from memory when the page is replaced in the buffer pool. Page writes associated with the eviction may be elided.

公开(公告)号：US10416931B2

公开(公告)日：2019-09-17

申请号：US15283211

申请日：2016-09-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Pradeep Fernando ,  Mijung Kim ,  Haris Volos ,  Jun Li

IPC: G06F3/06 ,  G06F11/14

Abstract: Examples herein involve fault tolerance in a shared memory. In examples herein, a metadata store of a shared memory indicating versions of data partitions of a resilient distributed dataset and a valid flag for the partitions of the resilient distributed dataset are used to achieve fault tolerance and/or recover from faults in the share memory.

公开(公告)号：US20170300412A1

公开(公告)日：2017-10-19

申请号：US15513407

申请日：2014-09-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Charles S. Johnson ,  Harumi Kuno ,  Goetz Graefe ,  Haris Volos ,  Mark Lillibridge ,  James Hyungsun Park ,  Wey Guy

IPC: G06F12/08 ,  G06F11/14 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F11/1446 ,  G06F11/1474 ,  G06F12/0868 ,  G06F12/12 ,  G06F2201/80 ,  G06F2212/1016

Abstract: Systems and methods associated with page modification are disclosed. One example method may be embodied on a non-transitory computer-readable medium storing computer-executable instructions. The instructions, when executed by a computer, may cause the computer to fetch a page to a buffer pool in a memory. The page may be fetched from at least one of a log and a backup using single page recovery. The instructions may also cause the computer to store a modification of the page to the log. The modification may be stored to the log as a log entry. The instructions may also cause the computer to evict the page from memory when the page is replaced in the buffer pool. Page writes associated with the eviction may be elided.

公开(公告)号：US10372602B2

公开(公告)日：2019-08-06

申请号：US15545901

申请日：2015-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0868

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US20180018258A1

公开(公告)日：2018-01-18

申请号：US15545901

申请日：2015-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/7203 ,  Y02D10/13

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US11144237B2

公开(公告)日：2021-10-12

申请号：US16529142

申请日：2019-08-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Milind M. Chabbi ,  Yupu Zhang ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1072 ,  G06F12/1081 ,  G06F13/00 ,  G06F13/28

Abstract: Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.

公开(公告)号：US10997064B2

公开(公告)日：2021-05-04

申请号：US16453784

申请日：2019-06-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0868

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US20190317891A1

公开(公告)日：2019-10-17

申请号：US16453784

申请日：2019-06-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02 ,  G06F12/0868 ,  G06F12/0804

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US10423464B2

公开(公告)日：2019-09-24

申请号：US15333820

申请日：2016-10-25

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Mark Lillibridge ,  Milind M. Chabbi ,  Haris Volos

IPC: G06F9/52 ,  G06F9/48 ,  G06F9/46 ,  G06F9/30

Abstract: In one example in accordance with the present disclosure, a method may include performing a transactional operation such that if one step of the transactional operation is performed, each other step of the transactional operation is performed. The transactional operation may include making a first copy, stored in a first persistent memory, of a next ticket number stored in a second persistent memory and updating the next ticket number in the second persistent memory. The method may also include determining when to serve a first thread based on the first copy of the next ticket number.

公开(公告)号：US10248493B2

公开(公告)日：2019-04-02

申请号：US15581882

申请日：2017-04-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Daniel Fryer ,  James Park ,  Haris Volos

IPC: G06F11/00 ,  G06F11/07

Abstract: Examples disclosed herein relate to determining that an operation is accessing data on a persistent memory and retrieving a log of the operation. The examples may also include determining a type of the data being accessed by the persistent memory by the operation and identifying, from the log, a location in the persistent memory of the data accessed by the operation. The examples may also include determining contents of the data accessed by the persistent memory by the operation and determining whether the contents of the data hold an invariant corresponding to the type of data.