公开(公告)号：US20090206442A1

公开(公告)日：2009-08-20

申请号：US12033322

申请日：2008-02-19

申请人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

发明人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L21/762 ,  H01L23/58

CPC分类号： H01L21/76232

摘要： A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.

摘要翻译： 一种形成用于半导体器件的浅沟槽隔离（STI）区域的方法，所述方法包括在半导体衬底内限定STI沟槽开口; 用初始沟槽填充材料填充STI沟槽开口; 在对应于STI沟槽开口的位置处限定衬底上的纳米尺度开口的图案; 将纳米级开口的图案转移到沟槽填充材料中，以便在沟槽填充材料中限定多个垂直取向的纳米级开口; 并用另外的沟槽填充材料堵塞纳米级开口的上部，从而在衬底中限定多孔STI区域。

公开(公告)号：US20090026574A1

公开(公告)日：2009-01-29

申请号：US11828718

申请日：2007-07-26

申请人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

发明人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T29/49107 ,  H01L2924/00

摘要： An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.

摘要翻译： 在半导体衬底上形成电熔丝和第一电介质层。 含有两个或更多个不同聚合物嵌段组分的自组装嵌段共聚物被施加到由电介质模板层包围的凹陷区域中。 然后将自组装嵌段共聚物退火以形成具有亚光刻直径的多个圆的图案。 通过反应离子蚀刻将多个圆圈的图案转移到第一介电层中，其中，在熔体上方的第一介电层的部分具有包括多个圆柱形孔的蜂窝图案。 通过非共形化学气相沉积在圆柱形孔上方形成第二介电层，并在融合体上形成亚光刻腔。 亚光刻腔相对于介质材料提供与熔丝相关的增强的热绝缘，使得电熔丝可以用较少的编程电流编程。

公开(公告)号：US08513769B2

公开(公告)日：2013-08-20

申请号：US12765275

申请日：2010-04-22

申请人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

发明人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

IPC分类号： H01L23/5256 ,  H01L23/5329 ,  H01L21/7682

CPC分类号： H01L23/5256 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

摘要翻译： 提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。 包括导体或半导体的导电结构形成在半导体衬底上。 在导电结构上形成至少一个绝缘体层。 在所述至少一个绝缘体层中形成凹陷区域。 将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。 第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。 具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。 形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

公开(公告)号：US08083958B2

公开(公告)日：2011-12-27

申请号：US11950600

申请日：2007-12-05

申请人： Wai-Kin Li ,  Haining S. Yang

发明人： Wai-Kin Li ,  Haining S. Yang

IPC分类号： B82Y40/00 ,  H01L21/302

CPC分类号： H01L21/0337 ,  G03F7/0035 ,  H01L21/0273 ,  H01L21/0334 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S977/888 ,  Y10S977/895

摘要： Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.

摘要翻译： 公开了包含光刻和自组装共聚物光刻技术的组合的光刻图案化方法的实施例，以便在衬底上形成具有多个单元的栅格图案掩模，每个栅格图案掩模具有至少一个小于50nm的尺寸。 不同光刻技术的组合进一步允许单个栅格图案单元与衬底内的对应结构的精确配准和覆盖。 然后可以结合定向蚀刻和其它工艺将所得到的网格图案掩模用于将单元图形延伸到基底中，从而形成具有至少一个次50nm尺寸的开口，着陆在相应的基底 结构。 一旦形成开口，可以在开口内形成附加结构。

公开(公告)号：US07871895B2

公开(公告)日：2011-01-18

申请号：US12033322

申请日：2008-02-19

申请人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

发明人： Ramachandra Divakaruni ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76232

摘要： A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.

摘要翻译： 一种形成用于半导体器件的浅沟槽隔离（STI）区域的方法，所述方法包括在半导体衬底内限定STI沟槽开口; 用初始沟槽填充材料填充STI沟槽开口; 在对应于STI沟槽开口的位置处限定衬底上的纳米尺度开口的图案; 将纳米级开口的图案转移到沟槽填充材料中，以便在沟槽填充材料中限定多个垂直取向的纳米级开口; 并用另外的沟槽填充材料堵塞纳米级开口的上部，从而在衬底中限定多孔STI区域。

公开(公告)号：US07825490B2

公开(公告)日：2010-11-02

申请号：US11779424

申请日：2007-07-18

申请人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

发明人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L29/93

CPC分类号： G11C17/16 ,  H01L21/76229 ,  H01L23/5256 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An electrical fuse is formed on a semiconductor substrate and a first dielectric layer is formed over the electrical fuse. At least one opening is formed by lithographic methods and a reactive ion etch in the first dielectric layer down to a top surface of the electrical fuse or down to shallow trench isolation. A second dielectric layer is deposited by a non-conformal deposition. Thickness of the second dielectric layer on the sidewalls of the at least one opening increases with height so that at least one cavity encapsulated by the second dielectric layer is formed in the at least one opening. The at least one cavity provides enhanced thermal isolation of the electrical fuse since the cavity provides superior thermal isolation than a dielectric material.

摘要翻译： 在半导体衬底上形成电熔丝，并在电熔丝上方形成第一电介质层。 至少一个开口通过光刻方法和第一电介质层中的反应离子蚀刻形成至电熔丝的顶表面或者至浅沟槽隔离。 通过非共形沉积沉积第二介电层。 至少一个开口的侧壁上的第二电介质层的厚度随着高度而增加，使得在至少一个开口中形成由第二介电层包封的至少一个空腔。 至少一个空腔提供了电熔丝的增强的热隔离，因为空腔提供比电介质材料更好的热隔离。

公开(公告)号：US07741721B2

公开(公告)日：2010-06-22

申请号：US11831236

申请日：2007-07-31

申请人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

发明人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

摘要翻译： 提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。 包括导体或半导体的导电结构形成在半导体衬底上。 在导电结构上形成至少一个绝缘体层。 在所述至少一个绝缘体层中形成凹陷区域。 将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。 第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。 具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。 形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

公开(公告)号：US07675137B2

公开(公告)日：2010-03-09

申请号：US11828718

申请日：2007-07-26

申请人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

发明人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L29/93

CPC分类号： H01L23/5256 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T29/49107 ,  H01L2924/00

摘要： An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.

摘要翻译： 在半导体衬底上形成电熔丝和第一电介质层。 含有两个或更多个不同聚合物嵌段组分的自组装嵌段共聚物被施加到由电介质模板层包围的凹陷区域中。 然后将自组装嵌段共聚物退火以形成具有亚光刻直径的多个圆的图案。 通过反应离子蚀刻将多个圆圈的图案转移到第一介电层中，其中，在熔体上方的第一介电层的部分具有包括多个圆柱形孔的蜂窝图案。 通过非共形化学气相沉积在圆柱形孔上方形成第二介电层，并在融合体上形成亚光刻腔。 亚光刻腔相对于介质材料提供与熔丝相关的增强的热绝缘，使得电熔丝可以用较少的编程电流编程。

公开(公告)号：US20090001045A1

公开(公告)日：2009-01-01

申请号：US11769126

申请日：2007-06-27

申请人： Kuang-Jung Chen ,  Wai-Kin Li ,  Haining S. Yang

发明人： Kuang-Jung Chen ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01B13/00

CPC分类号： B81C1/00031 ,  B81B2203/0315 ,  B81C2201/0149 ,  B82Y30/00 ,  H01L21/31144 ,  H01L21/7682 ,  H01L2221/1047

摘要： Methods of patterning a self-assembly nano-structure and forming a porous dielectric are disclosed. In one aspect, the method includes providing a hardmask over an underlying layer; predefining an area with a photoresist on the hardmask that is to be protected during the patterning; forming a layer of the copolymer over the hardmask and the photoresist; forming the self-assembly nano-structure from the copolymer; and etching to pattern the self-assembly nano-structure.

摘要翻译： 公开了自组装纳米结构图案化和形成多孔电介质的方法。 一方面，该方法包括在下层上提供硬掩模; 在图案化期间预定义在要被保护的硬掩模上的光致抗蚀剂的区域; 在硬掩模和光致抗蚀剂上形成共聚物层; 从共聚物形成自组装纳米结构; 并蚀刻以形成自组装纳米结构。

公开(公告)号：US20080308900A1

公开(公告)日：2008-12-18

申请号：US11761403

申请日：2007-06-12

申请人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

发明人： Deok-kee Kim ,  Wai-Kin Li ,  Haining S. Yang

IPC分类号： H01L29/00 ,  G03F1/00

CPC分类号： G03F1/40 ,  G03F1/36

摘要： A photolithography mask contains at least one sublithographic assist feature (SLAF) such that the image of the fuselink shape on a photoresist contains a constructive interference portion and two neck portions. The width of the constructive interference portion is substantially the same as a critical dimension of the lithography tool and the widths of the two neck portions are sublithographic dimensions. The image on a photoresist is subsequently transferred into an underlying semiconductor layer to form an electrical fuse. The fuselink contains a constructive interference portion having a first width which is substantially the same as the critical dimension of the lithography tool and two neck portions having sublithographic widths. The inventive electrical fuse may be programmed with less voltage bias, current, and energy compared to prior art electrical fuses.

摘要翻译： 光刻掩模包含至少一个亚光刻辅助特征（SLAF），使得光致抗蚀剂上的熔体形状的图像包含相长的干涉部分和两个颈部。 构造干涉部分的宽度基本上与光刻工具的临界尺寸相同，并且两个颈部的宽度是亚光刻尺寸。 随后将光致抗蚀剂上的图像转移到下面的半导体层中以形成电熔丝。 熔丝包含具有与光刻工具的临界尺寸基本相同的第一宽度和具有亚光刻宽度的两个颈部的构造干涉部分。 与现有技术的电熔丝相比，本发明的电熔丝可被编程为具有更少的电压偏置，电流和能量。