公开(公告)号：US08934311B2

公开(公告)日：2015-01-13

申请号：US13604308

申请日：2012-09-05

申请人： Hak-soo Yu ,  Uk-song Kang ,  Chul-woo Park ,  Joo-sun Choi ,  Hong-Sun Hwang

发明人： Hak-soo Yu ,  Uk-song Kang ,  Chul-woo Park ,  Joo-sun Choi ,  Hong-Sun Hwang

IPC分类号： G11C29/44 ,  G11C29/50 ,  G11C29/00 ,  G11C29/04 ,  G11C11/41

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/783 ,  G11C2029/0409 ,  G11C2029/4402

摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

摘要翻译： 半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

公开(公告)号：US08588017B2

公开(公告)日：2013-11-19

申请号：US13236972

申请日：2011-09-20

申请人： Chul-woo Park ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

发明人： Chul-woo Park ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G06F2213/0038 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C2211/4062

摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

摘要翻译： 存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作 命令。

公开(公告)号：US20120099389A1

公开(公告)日：2012-04-26

申请号：US13236972

申请日：2011-09-20

申请人： Chul-woo PARK ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

发明人： Chul-woo PARK ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

IPC分类号： G11C11/402 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808 ,  G06F2213/0038 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C2211/4062

摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

摘要翻译： 存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作 命令。

公开(公告)号：US08885380B2

公开(公告)日：2014-11-11

申请号：US13209026

申请日：2011-08-12

申请人： Uk-song Kang ,  Young-hyun Jun ,  Joo-sun Choi

发明人： Uk-song Kang ,  Young-hyun Jun ,  Joo-sun Choi

IPC分类号： G11C5/02 ,  H01L25/18 ,  G11C7/10

CPC分类号： H01L25/18 ,  G11C5/02 ,  G11C7/10 ,  H01L2224/48091 ,  H01L2225/06544 ,  H01L2924/00014

摘要： A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.

摘要翻译： 公开了半导体封装。 半导体封装包括封装接口，半导体芯片堆叠，多个通过衬底通孔的堆叠以及接口电路。 封装接口包括至少第一对端子。 每个通过衬底通孔的堆叠包括相应的半导体芯片的多个通过衬底通孔，每个穿过衬底经由电连接到直接相邻的半导体芯片的贯穿衬底通孔。 接口电路包括连接到第一对终端的输入端，以接收提供第一信息的差分信号，并且包括输出，以将包括单端信号格式的第一信息的输出信号提供给多个 通过衬底通孔的堆叠。

公开(公告)号：US20120059984A1

公开(公告)日：2012-03-08

申请号：US13209026

申请日：2011-08-12

申请人： Uk-song Kang ,  Young-hyun Jun ,  Joo-sun Choi

发明人： Uk-song Kang ,  Young-hyun Jun ,  Joo-sun Choi

IPC分类号： G06F12/10 ,  G11C7/00 ,  H01L23/48

CPC分类号： H01L25/18 ,  G11C5/02 ,  G11C7/10 ,  H01L2224/48091 ,  H01L2225/06544 ,  H01L2924/00014

摘要： A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.

摘要翻译： 公开了半导体封装。 半导体封装包括封装接口，半导体芯片堆叠，多个通过衬底通孔的堆叠以及接口电路。 封装接口包括至少第一对端子。 每个通过衬底通孔的堆叠包括相应的半导体芯片的多个通过衬底通孔，每个穿过衬底经由电连接到直接相邻的半导体芯片的贯穿衬底通孔。 接口电路包括连接到第一对终端的输入端，以接收提供第一信息的差分信号，并且包括输出，以将包括单端信号格式的第一信息的输出信号提供给多个 通过衬底通孔的堆叠。

公开(公告)号：US07538573B2

公开(公告)日：2009-05-26

申请号：US11705251

申请日：2007-02-12

申请人： Jae-kwan Kim ,  Joo-sun Choi

发明人： Jae-kwan Kim ,  Joo-sun Choi

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  H04L25/0278 ,  H04L25/0288

摘要： A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic impedance of a metal line connected to an external circuit, pre-emphasizes at least one input signal, and includes a control circuit and an output circuit. The control circuit matches the output impedance of the dynamic output circuit to the characteristic impedance of the metal line in response to at least one output signal, and outputs a plurality of resistor control signals which are used to pre-emphasize at least one input signal in response to the input signal. The output circuit controls the output impedance and pre-emphasizes the input signal in response to the resistor control signals, and outputs the output signal.

摘要翻译： 动态输出缓冲电路通过使用输入和输出信号来执行阻抗匹配功能和预加重功能，并且消耗相对较小的功率，占据相对较小的布局面积，并且动态地改变输出阻抗。 动态输出缓冲电路将输出阻抗与连接到外部电路的金属线的特性阻抗动态匹配，预先强调至少一个输入信号，并且包括控制电路和输出电路。 响应于至少一个输出信号，控制电路将动态输出电路的输出阻抗与金属线的特性阻抗相匹配，并输出多个电阻控制信号，用于预先强调至少一个输入信号 响应输入信号。 输出电路控制输出阻抗，并响应于电阻控制信号预加强输入信号，并输出输出信号。

公开(公告)号：US07986251B2

公开(公告)日：2011-07-26

申请号：US12547204

申请日：2009-08-25

申请人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

发明人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

IPC分类号： H03M5/00

CPC分类号： H03M5/06 ,  G11C7/1006

摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

摘要翻译： 输入/输出（IO）接口包括数据编码器，其对具有不同定时的多条并行数据中的每一条进行编码并产生多条编码数据;以及交流（AC）耦合传输单元，其传输多个 的交流耦合方法中的编码数据。 数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。 当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。 当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

公开(公告)号：US09036439B2

公开(公告)日：2015-05-19

申请号：US13548484

申请日：2012-07-13

申请人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

发明人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

IPC分类号： G11C29/08 ,  G11C7/00 ,  G11C29/50 ,  G11C11/406 ,  G11C5/04 ,  G11C11/40

CPC分类号： G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

摘要翻译： 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

公开(公告)号：US20070200592A1

公开(公告)日：2007-08-30

申请号：US11705251

申请日：2007-02-12

申请人： Jae-Kwan Kim ,  Joo-sun Choi

发明人： Jae-Kwan Kim ,  Joo-sun Choi

IPC分类号： H03K19/003

CPC分类号： H03K19/0005 ,  H04L25/0278 ,  H04L25/0288

摘要： A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic impedance of a metal line connected to an external circuit, pre-emphasizes at least one input signal, and includes a control circuit and an output circuit. The control circuit matches the output impedance of the dynamic output circuit to the characteristic impedance of the metal line in response to at least one output signal, and outputs a plurality of resistor control signals which are used to pre-emphasize at least one input signal in response to the input signal. The output circuit controls the output impedance and pre-emphasizes the input signal in response to the resistor control signals, and outputs the output signal.

摘要翻译： 动态输出缓冲电路通过使用输入和输出信号来执行阻抗匹配功能和预加重功能，并且消耗相对较少的功率，占据相对较小的布局面积，并且动态地改变输出阻抗。 动态输出缓冲电路将输出阻抗与连接到外部电路的金属线的特性阻抗动态匹配，预先强调至少一个输入信号，并且包括控制电路和输出电路。 响应于至少一个输出信号，控制电路将动态输出电路的输出阻抗与金属线的特性阻抗相匹配，并输出多个电阻控制信号，用于预先强调至少一个输入信号 响应输入信号。 输出电路控制输出阻抗，并响应于电阻控制信号预加强输入信号，并输出输出信号。

公开(公告)号：US10067681B2

公开(公告)日：2018-09-04

申请号：US13427625

申请日：2012-03-22

申请人： Chul-sung Park ,  Joo-sun Choi

发明人： Chul-sung Park ,  Joo-sun Choi

IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C7/10 ,  G11C8/10

摘要： A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.