摘要:
Methods and systems for operating internal systems of a vehicle are provided. Aspects include providing a field programmable gate array (FPGA), the FPGA including a communication channel port, wherein the communication channel port is operable to connect to one or more systems through a communication channel, and wherein the FPGA is configured to operate in one or more control modes, receiving a communication channel input to the communication channel port of the FPGA, based at least in part on the communication channel input, determining a control mode from the one or more control modes, and operating the FPGA in the control mode, wherein the control mode is associated with one system of the one or more systems.
摘要:
Providing collision avoidance protection to controllers sharing the same sensor. Each of a pair of asynchronous controllers changes the period of a sync pulse transmitted to the other controller to indicate to the other controller it is synchronized. When one of the controllers begins reading data from the shared sensor, the other controller waits to receive another sync pulse for indicating when the controller is finished reading data from the shared sensor. Thus, the asynchronous controllers avoid accessing the same sensor at the same time.
摘要:
A sensorless motor controller includes a variable link control, including a radiation-hardened field programmable gate array (FPGA) and a back electromotive force (EMF) decoder circuit. The back EMF decoder infers the position of a rotor of the motor. A filter on the decoder conditions the back EMF signal and has multiple cutoff frequencies which can be dynamically controlled by the FPGA in order to compensate for phase shift in the back EMF signal. The FPGA also controls a variable DC link and its digital speed control loop.
摘要:
Diagnosing whether controllers of internal vehicle systems are the source of failures detected by a system control managing a vehicle such as a spacecraft. Highspeed data is received via at a field programmable gate array (FPGA) embedded in an assembly of the vehicle. The FPGA includes a controller and a digital diagnostic interface. In one embodiment, the diagnostic interface utilizes Very Highspeed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) for performance modeling of a controller configured to control at least one internal system within the vehicle. The VHDL performance models the controller. Upon receiving an indication of a failure, the performance modeling of the controller is used to ascertain whether or not the controller is the source of the failure. Disassembly of the assembly housing the internal system is not required in order to ascertain whether or not the controller is the source of the failure.
摘要:
Diagnosing whether controllers of internal vehicle systems are the source of failures detected by a system control managing a vehicle such as a spacecraft. Highspeed data is received via at a field programmable gate array (FPGA) embedded in an assembly of the vehicle. The FPGA includes a controller and a digital diagnostic interface. In one embodiment, the diagnostic interface utilizes Very Highspeed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) for performance modeling of a controller configured to control at least one internal system within the vehicle. The VHDL performance models the controller. Upon receiving an indication of a failure, the performance modeling of the controller is used to ascertain whether or not the controller is the source of the failure. Disassembly of the assembly housing the internal system is not required in order to ascertain whether or not the controller is the source of the failure.
摘要:
Methods and systems for operating internal systems of a vehicle are provided. Aspects include providing a field programmable gate array (FPGA), the FPGA including a communication channel port, wherein the communication channel port is operable to connect to one or more systems through a communication channel, and wherein the FPGA is configured to operate in one or more control modes, receiving a communication channel input to the communication channel port of the FPGA, based at least in part on the communication channel input, determining a control mode from the one or more control modes, and operating the FPGA in the control mode, wherein the control mode is associated with one system of the one or more systems
摘要:
Providing collision avoidance protection to controllers sharing the same sensor. Each of a pair of asynchronous controllers changes the period of a sync pulse transmitted to the other controller to indicate to the other controller it is synchronized. When one of the controllers begins reading data from the shared sensor, the other controller waits to receive another sync pulse for indicating when the controller is finished reading data from the shared sensor. Thus, the asynchronous controllers avoid accessing the same sensor at the same time.
摘要:
An electromechanical system has a component to be positioned, a rotary permanent magnet motor for positioning the component, and sensors for determining an apparent position of the component based upon rotation of the permanent magnets. A control counts movement of the permanent magnets that pass the sensors in a desired direction and also in an undesired direction. The control reaches an actual position of the component based upon both directions of rotation. The control also compares the actual position to an expected position of the component and identifies a need to calibrate should a difference between the actual and expected positions differ by more than a determined amount. A method is also disclosed.
摘要:
A sensorless motor controller includes a variable link control, including a radiation-hardened field programmable gate array (FPGA) and a back electromotive force (EMF) decoder circuit. The back EMF decoder infers the position of a rotor of the motor. A filter on the decoder conditions the back EMF signal and has multiple cutoff frequencies which can be dynamically controlled by the FPGA in order to compensate for phase shift in the back EMF signal. The FPGA also controls a variable DC link and its digital speed control loop.