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    ELECTRODEPOSITION METHODS OF GALLIUM AND GALLIUM ALLOY FILMS AND RELATED PHOTOVOLTAIC STRUCTURES
    2.
    发明申请
    ELECTRODEPOSITION METHODS OF GALLIUM AND GALLIUM ALLOY FILMS AND RELATED PHOTOVOLTAIC STRUCTURES 审中-公开
    镓和镓合金膜的电沉积方法和相关的光伏结构

    公开(公告)号：US20120055612A1

    公开(公告)日：2012-03-08

    申请号：US12874496

    申请日：2010-09-02

    申请人： Shafaat Ahmed ,  Hariklia Deligianni ,  Qiang Huang ,  Kathleen B. Reuter ,  Lubomyr T. Romankiw ,  Raman Vaidyanathan

    发明人： Shafaat Ahmed ,  Hariklia Deligianni ,  Qiang Huang ,  Kathleen B. Reuter ,  Lubomyr T. Romankiw ,  Raman Vaidyanathan

    IPC分类号： C25D7/12 ,  B32B38/00 ,  C25D5/10

    CPC分类号： H01L31/0322 ,  C25D3/38 ,  C25D3/54 ,  C25D3/58 ,  C25D5/10 ,  C25D5/56 ,  C25D7/126 ,  H01L21/02568 ,  H01L21/02628 ,  H01L23/3738 ,  H01L31/0749 ,  H01L2224/73253 ,  Y02E10/541

    摘要： Photovoltaic devices and methods for preparing a p-type semiconductor layer for the photovoltaic devices generally include electroplating a layer of gallium or a gallium alloy onto a conductive layer by contacting the conductive layer with a plating bath free of complexing agents including a gallium salt, methane sulfonic acid or sodium sulfate and an organic additive comprising at least one nitrogen atom and/or at least one sulfur atom, and a solvent; adjusting a pH of the solution to be less than 2.6 or greater than 12.6. The photovoltaic device includes an impurity in the p-type semiconductor layer selected from the group consisting of arsenic, antimony, bismuth, and mixtures thereof. Various photovoltaic precursor layers for forming CIS, CGS and CIGS p-type semiconductor structures can be formed by electroplating the gallium or gallium alloys in this manner. Also disclosed are processes for forming a thermal interface of gallium or a gallium alloy with the electroplating process.

    摘要翻译： 用于制备用于光伏器件的p型半导体层的光伏器件和方法通常包括通过使导电层与不含络合剂的镀浴接触来将一层镓或镓合金电镀到导电层上，所述络合剂包括镓盐，甲烷 磺酸或硫酸钠和包含至少一个氮原子和/或至少一个硫原子的有机添加剂和溶剂; 调节溶液的pH值小于2.6或大于12.6。 光电器件包括选自砷，锑，铋及其混合物的p型半导体层中的杂质。 可以通过以这种方式电镀镓或镓合金来形成用于形成CIS，CGS和CIGS p型半导体结构的各种光伏前体层。 还公开了通过电镀工艺形成镓或镓合金的热界面的工艺。

    Forming a Photovoltaic Device
    5.
    发明申请
    Forming a Photovoltaic Device 审中-公开
    形成光伏器件

    公开(公告)号：US20110108115A1

    公开(公告)日：2011-05-12

    申请号：US12616745

    申请日：2009-11-11

    申请人： Hariklia Deligianni ,  Lubomyr T. Romankiw ,  Raman Vaidyanathan

    发明人： Hariklia Deligianni ,  Lubomyr T. Romankiw ,  Raman Vaidyanathan

    IPC分类号： H01L31/0296 ,  H01L31/18

    CPC分类号： H01L31/0322 ,  C25D3/56 ,  H01L31/18 ,  Y02E10/541

    摘要： Methods for forming photovoltaic devices, methods for forming semiconductor compounds, photovoltaic device and chemical solutions are presented. For example, a method for forming a photovoltaic device comprising a semiconductor layer includes forming the semiconductor layer by electrodeposition from an electrolyte solution. The electrolyte solution includes copper, indium, gallium, selenous acid (H2SeO3) and water.

    摘要翻译： 提出了形成光伏器件的方法，形成半导体化合物的方法，光伏器件和化学溶液。 例如，形成包含半导体层的光电器件的方法包括通过电解液的电沉积来形成半导体层。 电解质溶液包括铜，铟，镓，硒酸（H 2 SeO 3）和水。

    FORMATION OF VERTICAL DEVICES BY ELECTROPLATING
    8.
    发明申请
    FORMATION OF VERTICAL DEVICES BY ELECTROPLATING 有权
    通过电镀形成垂直装置

    公开(公告)号：US20090294989A1

    公开(公告)日：2009-12-03

    申请号：US12538782

    申请日：2009-08-10

    申请人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

    发明人： Hariklia Deligianni ,  Qiang Huang ,  John P. Hummel ,  Lubomyr T. Romankiw ,  Mary B. Rothwell

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76879 ,  H01L21/2885 ,  Y10S205/925

    摘要： The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

    摘要翻译： 本发明涉及通过电镀形成垂直导电结构的方法。 具体地，首先形成模板结构，其包括衬底，位于衬底表面上的离散金属接触焊盘，分立金属接触焊盘和衬底两者之间的级间电介质（ILD）层，以及金属通孔结构 延伸穿过ILD层到分立的金属接触垫上。 接下来，在模板结构中形成垂直通孔，其延伸穿过ILD层到分立的金属接触垫上。 然后通过电镀在垂直通孔中形成垂直导电结构，电镀通过通过金属通孔结构将电镀电流施加到离散的金属接触焊盘来进行。 优选地，模板结构包括多个分立的金属接触焊盘，多个金属通孔结构以及用于形成多个垂直导电结构的多个垂直通孔。

    OHMIC CONTACT OF THIN FILM SOLAR CELL
    9.
    发明申请
    OHMIC CONTACT OF THIN FILM SOLAR CELL 审中-公开
    薄膜太阳能电池的OHMIC接触

    公开(公告)号：US20140030843A1

    公开(公告)日：2014-01-30

    申请号：US13558383

    申请日：2012-07-26

    申请人： Shafaat Ahmed ,  Hariklia Deligianni ,  Lubomyr T. Romankiw

    发明人： Shafaat Ahmed ,  Hariklia Deligianni ,  Lubomyr T. Romankiw

    IPC分类号： H01L31/0264 ,  B82Y40/00

    CPC分类号： H01L31/022441 ,  B82Y30/00 ,  H01L31/022425 ,  H01L31/032 ,  H01L31/0322 ,  H01L31/0326 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/541

    摘要： A chalcogen-resistant material including at least one of a carbon nanotube layer and a high work function material layer is deposited on a transition metal layer on a substrate. A semiconductor chalcogenide/kesterite material layer is deposited over the chalcogen-resistant material. The carbon nanotubes, if present, can reduce contact resistance by providing direct electrically conductive paths from the transition metal layer through the chalcogen-resistant material and to the semiconductor chalcogenide material. The high work function material layer, if present, can reduce contact resistance by reducing chalcogenization of the transition metal in the transition metal layer. Reduction of the contact resistance can enhance efficiency of a solar cell including the chalcogenide semiconductor material.

    摘要翻译： 包含碳纳米管层和高功函数材料层中的至少一种的耐硫属材料沉积在基板上的过渡金属层上。 半导体硫族化物/凯斯特石材料层沉积在抗硫属材料上。 碳纳米管（如果存在）可以通过提供从过渡金属层通过硫属元素抵抗材料和半导体硫族化物材料的直接导电路径来降低接触电阻。 如果存在高功函数材料层，则可以通过减少过渡金属层中的过渡金属的硫族化来降低接触电阻。 降低接触电阻可以提高包括硫族化物半导体材料的太阳能电池的效率。

    Vertical nanowire FET devices
    10.
    发明授权
    Vertical nanowire FET devices 有权
    垂直纳米线FET器件

    公开(公告)号：US08637849B2

    公开(公告)日：2014-01-28

    申请号：US12984653

    申请日：2011-01-05

    申请人： Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw

    发明人： Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw

    IPC分类号： H01L29/06

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02521 ,  H01L21/02628 ,  H01L21/02639 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78642

    摘要： A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.

    摘要翻译： 形成在衬底上的垂直场效应晶体管（VFET），其上形成有导电底电极。 在其上方形成由栅电极包围的底部电介质隔离层和栅介质层。 以上是上隔离层。 孔在电极之间延伸穿过。 柱状垂直半导体纳米线（VSN）填充孔和顶部和底部电极之间。 在VSN的相对端处的掺杂源极和漏极区域之间的VSN的中心区域中形成FET沟道。 在底部电介质间隔层上方的VSN的外表面上形成的栅极电介质结构将VSN与栅电极分离。