公开(公告)号：US20070090902A1

公开(公告)日：2007-04-26

申请号：US11163485

申请日：2005-10-20

申请人： Hariklia Deligianni ,  Robert Edwards ,  Thomas Fleischman ,  Robert Groves ,  Charles Montrose ,  Richard Volant ,  Ping-Chuan Wang

发明人： Hariklia Deligianni ,  Robert Edwards ,  Thomas Fleischman ,  Robert Groves ,  Charles Montrose ,  Richard Volant ,  Ping-Chuan Wang

IPC分类号： H01H51/22

CPC分类号： H01H59/0009

摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。

公开(公告)号：US20050156695A1

公开(公告)日：2005-07-21

申请号：US11053732

申请日：2005-02-08

申请人： Panayotis Andricacos ,  L. Buchwalter ,  Hariklia Deligianni ,  Robert Groves ,  Christopher Jahnes ,  Jennifer Lund ,  Michael Meixner ,  David Seeger ,  Timothy Sullivan ,  Ping-Chuan Wang

发明人： Panayotis Andricacos ,  L. Buchwalter ,  Hariklia Deligianni ,  Robert Groves ,  Christopher Jahnes ,  Jennifer Lund ,  Michael Meixner ,  David Seeger ,  Timothy Sullivan ,  Ping-Chuan Wang

IPC分类号： H01H59/00 ,  H01H57/00 ,  H01L41/08 ,  H02N1/00

CPC分类号： H01H59/0009 ,  H01H2001/0078

摘要： A microelectromechanical switch including: at least one pair of actuator electrodes; at least one input electrode and at least one output electrode for input and output, respectively, of a radio frequency signal; and a beam movable by an attraction between the at least one pair of actuator electrodes, the movable beam having at least a portion electrically connected to the at least one input electrode and to the at least one output electrode when moved by the attraction between the at least one pair of actuator electrodes to make an electrical connection between the at least one input and output electrodes; wherein the at least one pair of actuator electrodes are electrically isolated from each of the at least one input and output electrodes. The microelectromechanical switch can be configured in single or multiple-poles and/or single or multiple throws.

公开(公告)号：US06639488B2

公开(公告)日：2003-10-28

申请号：US09948478

申请日：2001-09-07

申请人： Hariklia Deligianni ,  Robert Groves ,  Christopher Jahnes ,  Jennifer L. Lund ,  Panayotis Andricacos ,  John Cotte ,  L. Paivikki Buchwalter ,  David Seeger ,  Raul E. Acosta

发明人： Hariklia Deligianni ,  Robert Groves ,  Christopher Jahnes ,  Jennifer L. Lund ,  Panayotis Andricacos ,  John Cotte ,  L. Paivikki Buchwalter ,  David Seeger ,  Raul E. Acosta

IPC分类号： H01P110

CPC分类号： H01P1/12 ,  H01H59/0009 ,  H01H2059/0036

摘要： Disclosed is a capacitive electrostatic MEMS RF switch comprised of a lower electrode that acts as both a transmission line and as an actuation electrode. Also, there is an array of one or more fixed beams above the lower electrode that is connected to ground. The lower electrode transmits the RF signal when the top beam or beams are up and when the upper beams are actuated and bent down, the transmission line is shunted to ground ending the RF transmission. A high dielectric constant material is used in the capacitive portion of the switch to achieve a high capacitance per unit area thus reducing the required chip area and enhancing the insertion loss characteristics in the non-actuated state. A gap between beam and lower electrode of less than 1 &mgr;m is incorporated in order to minimize the electrostatic potential (pull-in voltage) required to actuate the switch.

摘要翻译： 公开了一种电容静电MEMS RF开关，其由作为传输线和致动电极两者的下电极组成。 此外，在下电极上方有一个或多个连接到地面的固定梁的阵列。 当顶部梁或梁向上时，下部电极发射RF信号，并且当上部梁被致动并向下弯曲时，传输线被分流到结束RF传输的地面。 在开关的电容部分中使用高介电常数材料以实现每单位面积的高电容，从而在非致动状态下减少所需的芯片面积并增强插入损耗特性。 引入小于1um的光束和下电极之间的间隙以便使致动开关所需的静电电位（拉入电压）最小化。

公开(公告)号：US20050245063A1

公开(公告)日：2005-11-03

申请号：US10709357

申请日：2004-04-29

申请人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01P11/00

CPC分类号： H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

摘要翻译： 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

公开(公告)号：US20060197119A1

公开(公告)日：2006-09-07

申请号：US11164765

申请日：2005-12-05

申请人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L29/80

CPC分类号： H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

摘要翻译： 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

公开(公告)号：US20060124927A1

公开(公告)日：2006-06-15

申请号：US10905013

申请日：2004-12-09

申请人： Robert Groves ,  Peter Gruber ,  Kevin Petrarca ,  Richard Volant ,  George Walker

发明人： Robert Groves ,  Peter Gruber ,  Kevin Petrarca ,  Richard Volant ,  George Walker

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H05K3/3468 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K3/325 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K2203/162 ,  H05K2203/167 ,  H01L2224/0401

摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.

摘要翻译： 公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。 导电结构包括通过注射成型的焊料形成的高纵横比结构。 本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。 该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。 此外，该方法可以向后兼容并可定制。

公开(公告)号：US20070190692A1

公开(公告)日：2007-08-16

申请号：US11275542

申请日：2006-01-13

申请人： Mete Erturk ,  Robert Groves ,  Jeffrey Johnson ,  Alvin Joseph ,  Qizhi Liu ,  Edmund Sprogis ,  Anthony Stamper

发明人： Mete Erturk ,  Robert Groves ,  Jeffrey Johnson ,  Alvin Joseph ,  Qizhi Liu ,  Edmund Sprogis ,  Anthony Stamper

IPC分类号： H01L21/50

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

摘要翻译： 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

公开(公告)号：US20090106713A1

公开(公告)日：2009-04-23

申请号：US11877155

申请日：2007-10-23

申请人： David S. Collins ,  Mete Erturk ,  Edward J. Gordon ,  Robert Groves ,  Robert M. Rassel

发明人： David S. Collins ,  Mete Erturk ,  Edward J. Gordon ,  Robert Groves ,  Robert M. Rassel

IPC分类号： G06F17/50

CPC分类号： H01L23/5225 ,  H01L21/823475 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/05 ,  H01L27/0688 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05093 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025

摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes active circuitry on a substrate, a bond pad carried by the substrate, and a shielding structure disposed between the substrate and the bond pad. The shielding structure includes a plurality of electrically characterized devices configured to reduce noise transmission from the active circuitry to the bond pad.

摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括衬底上的有源电路，由衬底承载的接合焊盘以及设置在衬底和焊盘之间的屏蔽结构。 屏蔽结构包括被配置为减少从有源电路到接合焊盘的噪声传输的多个电特征化器件。

公开(公告)号：US20090020856A1

公开(公告)日：2009-01-22

申请号：US11778902

申请日：2007-07-17

申请人： David S. Collins ,  Mete Erturk ,  Edward J. Gordon ,  Robert Groves ,  Robert M. Rassel

发明人： David S. Collins ,  Mete Erturk ,  Edward J. Gordon ,  Robert Groves ,  Robert M. Rassel

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/5225 ,  H01L23/552 ,  H01L23/642 ,  H01L24/05 ,  H01L27/0203 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025

摘要： Semiconductor device structures and methods for shielding a bond pad from electrical noise generated by active circuitry of an integrated circuit carried on a substrate. The structure includes electrically characterized devices placed in a pre-determined arrangement under the bond pad. The pre-determined arrangement of the electrically characterized devices provides for a consistent high frequency environment under the bond pad, which simplifies modeling of the bond pad by a circuit designer.

摘要翻译： 用于屏蔽接合焊盘的电子器件结构和方法，其由承载在衬底上的集成电路的有源电路产生的电噪声。 该结构包括以特定的布置放置在接合焊盘下方的电特征化器件。 电气特征化器件的预定布置提供了在焊盘下方的一致的高频环境，这简化了电路设计者对接合焊盘的建模。

公开(公告)号：US20050034885A1

公开(公告)日：2005-02-17

申请号：US10604706

申请日：2003-08-12

申请人： Robert Groves ,  Jae-Eun Park

发明人： Robert Groves ,  Jae-Eun Park

IPC分类号： H01F17/00 ,  H01L23/522 ,  H05K1/02 ,  H05K1/16 ,  H05K9/00

CPC分类号： H01L23/5227 ,  H01F2017/008 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/165 ,  H01L2924/00

摘要： Three dimensional dynamically shielded high quality factor (Q) BEOL metal elements, such as inductor elements, are disclosed. Three dimensional shielding structures for the BEOL elements reduce or eliminate parasitic substrate capacitive coupling between the BEOL element and the conductive substrate, and parasitic shunt capacitance coupling between different adjacent shunt sections of the BEOL element. The reduction or elimination of the parasitic capacitive components provides high Q BEOL metal elements such as inductor elements. The three dimensional shield structure includes a lower shield surface having a width greater than the width of the BEOL element, and opposed side shield surfaces which extend upwardly from opposite side edges of the lower shield surface, such that the three dimensional shield element forms a U shaped shield around the BEOL element. The three dimensional shield element is dynamically driven to the same electrical potential as the BEOL element, to substantially eliminate the metal element's parasitic capacitances.

摘要翻译： 公开了三维动态屏蔽高品质因数（Q）BEOL金属元件，如电感元件。 用于BEOL元件的三维屏蔽结构降低或消除了BEOL元件与导电衬底之间的寄生衬底电容耦合，以及BEOL元件的不同相邻分流段之间的寄生并联电容耦合。 寄生电容元件的减少或消除提供高Q BEOL金属元件，如电感元件。 三维屏蔽结构包括具有大于BEOL元件的宽度的宽度的下屏蔽表面以及从下屏蔽表面的相对侧边缘向上延伸的相对侧屏蔽表面，使得三维屏蔽元件形成U BEOL元件周围形状的屏蔽。 三维屏蔽元件被动态地驱动到与BEOL元件相同的电位，以基本上消除金属元件的寄生电容。