公开(公告)号：US20050055505A1

公开(公告)日：2005-03-10

申请号：US10655365

申请日：2003-09-04

申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F12/00 ,  G06F12/12

CPC分类号： G06F12/126

摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

公开(公告)号：US20070052562A1

公开(公告)日：2007-03-08

申请号：US11191580

申请日：2005-07-28

申请人： Harm Hofstee ,  James Kahle ,  Takeshi Yamazaki

发明人： Harm Hofstee ,  James Kahle ,  Takeshi Yamazaki

IPC分类号： H03M7/40

CPC分类号： G06F17/5045

摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.

摘要翻译： 公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。 该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。 对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。 这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。 给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。 任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

公开(公告)号：US20050055507A1

公开(公告)日：2005-03-10

申请号：US10655367

申请日：2003-09-04

申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F12/00 ,  G06F12/12

CPC分类号： G06F12/126

摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

公开(公告)号：US20070168538A1

公开(公告)日：2007-07-19

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

公开(公告)号：US20070174509A1

公开(公告)日：2007-07-26

申请号：US11695436

申请日：2007-04-02

申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  Peichum Liu ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  Peichum Liu ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.

摘要翻译： 本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。 计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。 标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。 并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

公开(公告)号：US20060149861A1

公开(公告)日：2006-07-06

申请号：US11029891

申请日：2005-01-05

申请人： Takeshi Yamazaki ,  Tsutomu Horikawa ,  James Kahle ,  Charles Johns ,  Michael Day ,  Peichun Liu

发明人： Takeshi Yamazaki ,  Tsutomu Horikawa ,  James Kahle ,  Charles Johns ,  Michael Day ,  Peichun Liu

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

摘要翻译： 方法和装置提供了响应于处理器向直接存储器访问控制器（DMAC）发出的单个DMA命令，在处理器的共享存储器和本地存储器之间传送多个数据块，其中处理器能够操作 与共享存储器和DMAC的通信可操作地耦合到本地存储器。

公开(公告)号：US08996440B2

公开(公告)日：2015-03-31

申请号：US13474159

申请日：2012-05-17

申请人： Takeshi Yamazaki ,  Seiji Wada ,  Yoshihiro Wakita ,  Koji Kashima ,  Natsuki Kimura

发明人： Takeshi Yamazaki ,  Seiji Wada ,  Yoshihiro Wakita ,  Koji Kashima ,  Natsuki Kimura

IPC分类号： G06N5/02 ,  G06Q10/10

CPC分类号： G06Q10/109

摘要： An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.

摘要翻译： 被配置为创建要呈现给用户的日程表的信息处理设备包括估计单元和创建单元。 估计单元被配置为估计用户是否根据包括要完成预设目标的任务的第一调度进行动作。 创建单元被配置为当估计用户不按照第一时间表行动时创建新的第二计划，用于从不遵循第一进度的行为的用户的状态完成目标。

公开(公告)号：US08774895B2

公开(公告)日：2014-07-08

申请号：US13616185

申请日：2012-09-14

申请人： Seiji Wada ,  Takeshi Yamazaki ,  Natsuki Kimura ,  Yoshihiro Wakita ,  Koji Kashima ,  Tomiji Tanaka ,  Mitsuhiro Nakamura ,  Tatsumi Sakaguchi ,  Haruhiko Soma ,  Takuro Yamamoto

发明人： Seiji Wada ,  Takeshi Yamazaki ,  Natsuki Kimura ,  Yoshihiro Wakita ,  Koji Kashima ,  Tomiji Tanaka ,  Mitsuhiro Nakamura ,  Tatsumi Sakaguchi ,  Haruhiko Soma ,  Takuro Yamamoto

IPC分类号： A61B5/0478 ,  A61B5/00

CPC分类号： A61B5/0478 ,  A61B5/6803 ,  A61B5/6814 ,  A61B5/6843

摘要： An electroencephalographic headset includes: a supporter that includes expanding and contracting wires each having expansion and contraction properties and is to be attached to a head of a user by expansion and contraction of each of the expanding and contracting wires; and a plurality of electrodes that are provided to the supporter in defined placement.

摘要翻译： 脑电耳机包括：支撑件，其包括每个具有伸缩性能的伸缩线，并且通过每个伸缩线的伸缩来附接到使用者的头部; 以及以规定的位置设置在支撑体上的多个电极。

公开(公告)号：US08761554B2

公开(公告)日：2014-06-24

申请号：US13419646

申请日：2012-03-14

申请人： Koji Matsumoto ,  Satoshi Watanabe ,  Toshiro Okamura ,  Takeshi Yamazaki

发明人： Koji Matsumoto ,  Satoshi Watanabe ,  Toshiro Okamura ,  Takeshi Yamazaki

IPC分类号： G02B6/26 ,  G02B6/42

CPC分类号： G02B6/3518 ,  G02B6/3534

摘要： Provided is a wavelength selective switch, which includes: an input/output unit; a dispersive portion; a condensing optical system; and the deflection portion. The input/output unit has input/output ports. The dispersive portion disperses signal light incident from the input/output ports. The condensing optical system condenses a plurality of signal light beams dispersed by the dispersive portion. The deflection portion has a plurality of deflection elements. The deflection elements deflect, along a second direction, the signal light beams condensed by the condensing optical system. In the condensing optical system, the aberration amount of the meridional component in a sagittal coma aberration remains substantially constant irrespective of an angle formed between the optical axis of the condensing optical system and a signal light beam incident on the condensing optical system from the input/output portion, at an incident position of the incident signal light beam at a certain height in the second direction.

摘要翻译： 提供一种波长选择开关，其包括：输入/输出单元; 分散部分; 聚光光学系统; 和偏转部。 输入/输出单元具有输入/输出端口。 色散部分分散从输入/输出端口入射的信号光。 聚光光学系统凝聚由分散部分散射的多个信号光束。 偏转部分具有多个偏转元件。 偏转元件沿着第二方向偏转由聚光光学系统会聚的信号光束。 在聚光光学系统中，与聚光光学系统的光轴和入射到聚光光学系统的信号光束之间的角度不同，矢状彗差中的子午分量的像差量保持基本恒定， 在入射信号光束的入射位置处，在第二方向上处于一定高度。

公开(公告)号：US20120310873A1

公开(公告)日：2012-12-06

申请号：US13474159

申请日：2012-05-17

申请人： Takeshi Yamazaki ,  Seiji Wada ,  Yoshihiro Wakita ,  Koji Kashima ,  Natsuki Kimura

发明人： Takeshi Yamazaki ,  Seiji Wada ,  Yoshihiro Wakita ,  Koji Kashima ,  Natsuki Kimura

IPC分类号： G06N5/02

CPC分类号： G06Q10/109

摘要： An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.

摘要翻译： 被配置为创建要呈现给用户的日程表的信息处理设备包括估计单元和创建单元。 估计单元被配置为估计用户是否根据包括要完成预设目标的任务的第一调度进行动作。 创建单元被配置为当估计用户不按照第一时间表行动时创建新的第二计划，用于从不遵循第一进度的行为的用户的状态完成目标。