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    Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions
    3.
    发明申请
    Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions 审中-公开
    使用硬件事务原语在事务内部实现非事务性转义操作

    公开(公告)号：US20130013899A1

    公开(公告)日：2013-01-10

    申请号：US13176833

    申请日：2011-07-06

    申请人： Christopher M. Barton ,  Harold W. Cain, III ,  Bradly G. Frey ,  Hung Q. Le ,  Maged M. Michael ,  Raul E. Silvera ,  Derek E. Williams ,  Michael Wong ,  Peng Wu

    发明人： Christopher M. Barton ,  Harold W. Cain, III ,  Bradly G. Frey ,  Hung Q. Le ,  Maged M. Michael ,  Raul E. Silvera ,  Derek E. Williams ,  Michael Wong ,  Peng Wu

    IPC分类号： G06F9/30

    CPC分类号： G06F9/466

    摘要： Mechanisms are provided for performing escape actions within transactions. These mechanisms execute a transaction comprising a transactional section and an escape action. The transactional section is comprised of one or more instructions that are to be executed in an atomic manner as part of the transaction. The escape action is comprised of one or more instructions to be executed in a non-transactional manner. These mechanisms further populate at least one actions list data structure, associated with a thread of the data processing system that is executing the transaction, with one or more actions associated with the escape action. Moreover, these mechanisms execute one or more actions in the actions list data structure based upon whether the transaction commits successfully or is aborted.

    摘要翻译： 提供了在事务中执行转义操作的机制。 这些机制执行包括事务部分和转义动作的事务。 事务部分由作为事务的一部分以原子方式执行的一个或多个指令组成。 转义动作由以非事务方式执行的一个或多个指令组成。 这些机制进一步填充与执行交易的数据处理系统的线程相关联的至少一个动作列表数据结构，其中一个或多个动作与转义动作相关联。 此外，这些机制基于事务提交成功还是中止，在动作列表数据结构中执行一个或多个动作。

    Transactional memory preemption mechanism
    4.
    发明授权
    Transactional memory preemption mechanism 失效
    事务记忆抢占机制

    公开(公告)号：US08544022B2

    公开(公告)日：2013-09-24

    申请号：US13465115

    申请日：2012-05-07

    申请人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

    发明人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

    IPC分类号： G06F9/46 ,  G06F15/00 ,  G06F11/00 ,  G06F13/24

    CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

    摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

    摘要翻译： 提供了在数据处理系统中执行事务的机制。 在处理器的内部寄存器中生成事务检查点数据结构。 事务检查点数据结构存储表示执行相应事务之前的时间的程序寄存器的状态的事务检查点数据。 执行包括由处理器执行的代码的第一部分的事务。 在执行事务时接收事务的中断，结果，事务检查点数据被存储到数据处理系统的存储器中的数据结构。 然后执行第二部分代码。 响应于发生的事件导致处理器的执行切换返回到事务的执行，使用数据处理系统的存储器中的数据结构恢复程序寄存器的状态。

    Transactional memory preemption mechanism
    5.
    发明授权
    Transactional memory preemption mechanism 失效

    公开(公告)号：US08424015B2

    公开(公告)日：2013-04-16

    申请号：US12894308

    申请日：2010-09-30

    申请人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

    发明人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

    IPC分类号： G06F9/46 ,  G06F15/00 ,  G06F11/00 ,  G06F13/24

    CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

    摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

    Transactional Memory Preemption Mechanism
    6.
    发明申请
    Transactional Memory Preemption Mechanism 失效

    公开(公告)号：US20120246658A1

    公开(公告)日：2012-09-27

    申请号：US13465115

    申请日：2012-05-07

    申请人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

    发明人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

    IPC分类号： G06F9/46

    CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

    摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

    Transactional Memory Preemption Mechanism
    7.
    发明申请
    Transactional Memory Preemption Mechanism 失效
    事务记忆抢占机制

    公开(公告)号：US20120084477A1

    公开(公告)日：2012-04-05

    申请号：US12894308

    申请日：2010-09-30

    申请人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

    发明人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

    IPC分类号： G06F13/24

    CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

    摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

    摘要翻译： 提供了在数据处理系统中执行事务的机制。 在处理器的内部寄存器中生成事务检查点数据结构。 事务检查点数据结构存储表示执行相应事务之前的时间的程序寄存器的状态的事务检查点数据。 执行包括由处理器执行的代码的第一部分的事务。 在执行事务时接收事务的中断，结果，事务检查点数据被存储到数据处理系统的存储器中的数据结构。 然后执行第二部分代码。 响应于发生的事件导致处理器的执行切换返回到事务的执行，使用数据处理系统的存储器中的数据结构恢复程序寄存器的状态。

    Detection of conflicts between transactions and page shootdowns
    8.
    发明授权
    Detection of conflicts between transactions and page shootdowns 有权
    检测事务和页面冲突之间的冲突

    公开(公告)号：US09086986B2

    公开(公告)日：2015-07-21

    申请号：US13606743

    申请日：2012-09-07

    申请人： Harold W. Cain, III ,  Hung Q. Le ,  Bryan Lloyd ,  Shih-Hsiung Tung

    发明人： Harold W. Cain, III ,  Hung Q. Le ,  Bryan Lloyd ,  Shih-Hsiung Tung

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

    摘要： There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages.

    摘要翻译： 提供了一种用于检测事务和事务存储器中的TLB（翻译后备缓冲器）冲突之间的冲突的方法，其中处理器接收到TLB击倒操作消息以使处理器的TLB中的至少一个条目相应对应 至少一页。 处理器跟踪事务触摸的页面。 处理器确定接收的TLB拍摄操作消息是否与所触摸的页面中的一个相关联。 响应于确定接收到的TLB击倒操作消息与所触摸的页面之一相关联，处理器中止该事务。

    HARDWARE ASSISTED SCHEDULING IN COMPUTER SYSTEM
    9.
    发明申请
    HARDWARE ASSISTED SCHEDULING IN COMPUTER SYSTEM 审中-公开
    计算机系统中的硬件辅助调度

    公开(公告)号：US20120284720A1

    公开(公告)日：2012-11-08

    申请号：US13102389

    申请日：2011-05-06

    申请人： Harold W. Cain, III ,  Hubertus Franke ,  Charles R. Johns ,  James A. Kahle ,  Hung Q. Le ,  Ravi Nair

    发明人： Harold W. Cain, III ,  Hubertus Franke ,  Charles R. Johns ,  James A. Kahle ,  Hung Q. Le ,  Ravi Nair

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4881 ,  G06F2209/5018

    摘要： Apparatus and methods for hardware assisted scheduling of software tasks in a computer system are disclosed. For example, a computer system comprises a first pool for maintaining a set of executable software threads, a first scheduler, a second pool for maintaining a set of active software threads, and a second scheduler. The first scheduler assigns a subset of the set of executable software threads to the set of active software threads and the second scheduler dispatches one or more threads from the set of active software threads to a set of hardware threads for execution. In one embodiment, the first scheduler is implemented as part of the operating system of the computer system, and the second scheduler is implemented in hardware.

    摘要翻译： 公开了一种用于计算机系统中的软件任务的硬件辅助调度的装置和方法。 例如，计算机系统包括用于维护一组可执行软件线程的第一池，第一调度器，用于维护一组活动软件线程的第二池和第二调度器。 第一调度器将该组可执行软件线程的子集分配给该组活动软件线程，并且第二调度器将一个或多个线程从该组活动软件线程调度到一组用于执行的硬件线程。 在一个实施例中，第一调度器被实现为计算机系统的操作系统的一部分，并且第二调度器以硬件实现。

    DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS
    10.
    发明申请
    DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS 有权
    检测交易与信息页之间的冲突

    公开(公告)号：US20140075151A1

    公开(公告)日：2014-03-13

    申请号：US13606743

    申请日：2012-09-07

    申请人： Harold W. Cain, III ,  Hung Q. Le ,  Bryan Lloyd ,  Shih-Hsiung Tung

    发明人： Harold W. Cain, III ,  Hung Q. Le ,  Bryan Lloyd ,  Shih-Hsiung Tung

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

    摘要： There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages.

    摘要翻译： 提供了一种用于检测事务和事务存储器中的TLB（翻译后备缓冲器）冲突之间的冲突的方法，其中处理器接收到TLB击倒操作消息以使处理器的TLB中的至少一个条目相应对应 至少一页。 处理器跟踪事务触摸的页面。 处理器确定接收的TLB拍摄操作消息是否与所触摸的页面中的一个相关联。 响应于确定接收到的TLB击倒操作消息与所触摸的页面之一相关联，处理器中止该事务。