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41 条记录 (耗时 0.018 秒)

    High impedance detecting circuit and interface circuit
    1.
    发明授权
    High impedance detecting circuit and interface circuit 失效
    高阻抗检测电路和接口电路

    公开(公告)号：US5874835A

    公开(公告)日：1999-02-23

    申请号：US719888

    申请日：1996-09-25

    申请人： Masahiko Ishiwaki ,  Harufusa Kondoh ,  Hiromi Notani

    发明人： Masahiko Ishiwaki ,  Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： G01R31/317 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  H03K19/02

    CPC分类号： H03K19/003

    摘要： A voltage applying means applies a voltage which determines the logical value of a node to the node, with the signal at the node fixed. Then, an applied voltage removing means removes the voltage applied by the voltage applying means. First and second detecting means detects the logical value of the node before and after the voltage application and removal of the applied voltage. A judging means compares the results of detection of the first and second detecting means to judge whether or not the node is at a high impedance.

    摘要翻译： 电压施加装置将确定节点的逻辑值的电压施加到节点，同时节点处的信号被固定。 然后，施加的电压去除装置去除由电压施加装置施加的电压。 第一和第二检测装置检测在施加电压和施加的电压的去除之前和之后节点的逻辑值。 判断装置比较第一和第二检测装置的检测结果，以判断节点是否处于高阻抗。

    Digital data transmission system
    2.
    发明授权
    Digital data transmission system 失效
    数字数据传输系统

    公开(公告)号：US06396888B1

    公开(公告)日：2002-05-28

    申请号：US09032944

    申请日：1998-03-02

    申请人： Hiromi Notani ,  Harufusa Kondoh ,  Masahiko Ishiwaki ,  Tsutomu Yoshimura

    发明人： Hiromi Notani ,  Harufusa Kondoh ,  Masahiko Ishiwaki ,  Tsutomu Yoshimura

    IPC分类号： H04L706

    CPC分类号： H03L7/0805 ,  H03L7/0812 ,  H03L7/0891 ,  H04J3/0614 ,  H04L7/0008 ,  H04L7/02 ,  H04L7/04

    摘要： A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

    摘要翻译： 提供了一种用于使用所需的最小数量的信号线和简单的电路结构来发送数字数据，帧脉冲信号和时钟的数字数据传输系统。 接收与时钟（CK）复用的帧脉冲信号（FP）的多时钟（CKFP）的信号分离电路（46）包括：时钟恢复电路（47），用于通过与时钟（CK）同步再现再生时钟（RCK） 使用同步环路的多个时钟（CKFP）和基于恢复时钟（RCK）从多个时钟（CKFP）分离恢复的帧脉冲信号（RFP）的帧脉冲信号分离电路（48）。

    Waveform shaping device and clock supply apparatus
    4.
    发明授权
    Waveform shaping device and clock supply apparatus 失效
    波形整形装置及时钟提供装置

    公开(公告)号：US5883534A

    公开(公告)日：1999-03-16

    申请号：US747076

    申请日：1996-11-08

    申请人： Harufusa Kondoh ,  Masahiko Ishiwaki ,  Hiromi Notani

    发明人： Harufusa Kondoh ,  Masahiko Ishiwaki ,  Hiromi Notani

    IPC分类号： H03K5/125 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K3/017 ,  H03K3/02 ,  H03K5/00 ,  H03K5/13 ,  H03K5/156 ,  H03K7/08 ,  H03K17/04 ,  H03L7/00 ,  H03L7/081 ,  H03L7/06

    CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/1565 ,  H03K7/08 ,  H03L7/0812 ,  H03L7/0814

    摘要： The operating speed of an apparatus which operates with a clock is increased by obtaining a clock having a constant duty ratio. The maximum variable delay quantity of a first variable delay circuit 11 is set more than one cycle and less than two cycles of an input clock IN. The delay quantities of the first and second variable delay circuits 11, 12 are decreased with a control signal Vin. In addition, the ratio of the delay quantity of the second variable delay circuit 12 to that of the first variable delay circuit 11 is set to a constant value which is less than 1. A control portion 13 increases and decreases the control signal Vin in such a manner that the phases of an input clock IN and an output clock OUT-A of the first variable delay circuit are coincident with each other. An output clock OUT of the device is set by the output clock OUT-A of the first variable delay circuit, and is reset by an output clock OUT-B of the second variable delay circuit. Consequently, the output clock of the device has the same phase as that of the input clock IN and a constant duty ratio.

    摘要翻译： 通过获得具有恒定占空比的时钟来增加用时钟操作的装置的操作速度。 第一可变延迟电路11的最大可变延迟量被设定为输入时钟IN的多于一个周期且小于两个周期。 第一和第二可变延迟电路11,12的延迟量随着控制信号Vin而减小。 此外，第二可变延迟电路12的延迟量与第一可变延迟电路11的延迟量的比率被设置为小于1的常数值。控制部分13增加和减少控制信号Vin 第一可变延迟电路的输入时钟IN和输出时钟OUT-A的相位彼此一致的方式。 器件的输出时钟OUT由第一可变延迟电路的输出时钟OUT-A设置，并由第二可变延迟电路的输出时钟OUT-B复位。 因此，器件的输出时钟具有与输入时钟IN相同的相位和恒定占空比。

    Network communication device
    5.
    发明授权
    Network communication device 失效
    网络通信设备

    公开(公告)号：US06195361B1

    公开(公告)日：2001-02-27

    申请号：US08957366

    申请日：1997-10-24

    申请人： Harufusa Kondoh ,  Masahiko Ishiwaki

    发明人： Harufusa Kondoh ,  Masahiko Ishiwaki

    IPC分类号： H04L1254

    CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/309 ,  H04L2012/5647 ,  H04L2012/5651 ,  H04Q11/0478

    摘要： A network communication device which can discard invalid packets at once is obtained. A plurality of cells received from input lines (IN#1-4) are stored in a shared buffer memory (SBM) and a control portion (CTL) manages tags and addresses. Among the received cells stored in the shared buffer memory (SBM), ones corresponding to discarded management data are not identified. Accordingly, virtually, the received cells in the shared buffer memory (SBM) can be discarded at once.

    摘要翻译： 获得可以一次丢弃无效数据包的网络通信设备。 从输入线（IN＃1-4）接收的多个单元被存储在共享缓冲存储器（SBM）中，控制部分（CTL）管理标签和地址。 在存储在共享缓冲存储器（SBM）中的接收到的单元中，不识别对应于丢弃的管理数据的单元。 因此，虚拟地，可以一次丢弃共享缓冲存储器（SBM）中接收到的单元。

    Output circuit and interface system comprising the same
    6.
    发明授权
    Output circuit and interface system comprising the same 失效
    输出电路和包含它的接口系统

    公开(公告)号：US5235222A

    公开(公告)日：1993-08-10

    申请号：US813627

    申请日：1991-12-26

    申请人： Harufusa Kondoh ,  Hiromi Notani

    发明人： Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： H04L25/02 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H04Q3/42

    CPC分类号： H03K19/00361 ,  H03K19/018557

    摘要： An output circuit 1 comprises a constant current source 11, a switch 12, and an output pad 14. The switch 12 is connected between the constant current source 11 and the output pad 14. A transmission path 3 is connected to the output pad 14. The transmission path 3 is coupled to a terminator voltage V.sub.TT by a resistor for pull up. Reflection of a signal or generation of noise can be suppressed by bringing the resistance value of the resistor 4 close to a characteristic impedance of the transmission path 3. A voltage amplitude on the transmission path 3 can be determined arbitrarily by adjusting current value of the constant current source 11 and resistance value of the resistor 4.

    摘要翻译： 输出电路1包括恒流源11，开关12和输出垫14.开关12连接在恒流源11和输出垫14之间。传输路径3连接到输出焊盘14。 传输路径3通过用于上拉的电阻器耦合到终端电压VTT。 可以通过使电阻器4的电阻值接近传输路径3的特性阻抗来抑制信号的反射或产生噪声。传输路径3上的电压振幅可以通过调整常数的电流值来任意确定 电流源11和电阻器4的电阻值。

    Clock-synchronized C-element group for controlling data transfer
    7.
    发明授权
    Clock-synchronized C-element group for controlling data transfer 失效
    时钟同步C元素组，用于控制数据传输

    公开(公告)号：US5724562A

    公开(公告)日：1998-03-03

    申请号：US559654

    申请日：1995-11-20

    申请人： Masahiko Ishiwaki ,  Harufusa Kondoh

    发明人： Masahiko Ishiwaki ,  Harufusa Kondoh

    IPC分类号： G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G06F5/06 ,  G06F9/38 ,  G06F1/04

    CPC分类号： G06F9/3869

    摘要： Flows of data are controlled using an externally supplied clock. A clock-synchronized C-element C1 outputs a sending signal S1 of H level to a data latch DL1 and the subsequent clock-synchronized C-element C2 and outputs an acknowledge signal A1 of H level, in synchronization with a rise of a clock signal CLK1 which is inputted to the clock-synchronized C-element C1 after the clock-synchronized C-element C1 receives a sending signal S0 of H level. Following this, the clock-synchronized C-element C1 causes the acknowledge signal A1 to fall by the next rise of the clock signal CLK1. This latches the data latch DL1. A clock signal CLK2 rises before the clock signal CLK1 falls and rises once again. In synchronization with this rise, the clock-synchronized C-element C2 performs a similar operation. As a result, the precedent clock-synchronized C-element C1 causes the sending signal S1 to fall.

    摘要翻译： 使用外部提供的时钟控制数据流。 时钟同步C元件C1将H电平的发送信号S1输出到数据锁存器DL1和随后的时钟同步C元件C2，并与时钟信号的上升同步地输出H电平的确认信号A1 CLK1，其在时钟同步C元件C1接收到H电平的发送信号S0之后被输入到时钟同步的C元件C1。 此后，时钟同步的C元件C1使得确认信号A1下降到时钟信号CLK1的下一个上升沿。 这将锁存数据锁存器DL1。 时钟信号CLK2在时钟信号CLK1下降之前上升，并再次上升。 与此同步，时钟同步的C元件C2执行类似的操作。 结果，先前的时钟同步C元件C1使发送信号S1下降。

    Method of testing switches and switching circuit
    9.
    发明授权
    Method of testing switches and switching circuit 失效
    开关和开关电路的测试方法

    公开(公告)号：US5347270A

    公开(公告)日：1994-09-13

    申请号：US889379

    申请日：1992-05-28

    申请人： Yoshio Matsuda ,  Harufusa Kondoh ,  Isamu Hayashi ,  Hiromi Notani

    发明人： Yoshio Matsuda ,  Harufusa Kondoh ,  Isamu Hayashi ,  Hiromi Notani

    IPC分类号： H01L27/10 ,  H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04Q1/24 ,  H04Q11/04 ,  H04L12/26 ,  H04M3/26

    CPC分类号： H04Q11/0421 ,  H04L49/104 ,  H04Q1/245 ,  H04Q11/0478 ,  H04L2012/5628

    摘要： Incoming lines (I0 to I7) are connected to a space switch (2) through input data latches (1). The space switch (2) is connected to a normal/test changeover switch (12), which is connected to a normal/test changeover switch (13) through serial-to-parallel converting circuits (3), common buffer memories (4) and parallel-to-serial converting circuits (5). Space switches (6) are connected to the normal/test changeover switch (13). Outgoing lines (O0 to O7) are connected to the space switches 6 through output data latches (8). Connection states in the switches (2, 6) are placed in transposed relation to each other by a transposed connection generating circuit (10) in a test operation, so that the switches (2, 6) are directly connected to each other through the switches (12, 13). Predetermined data applied to the incoming lines are intactly used as expected values for judgement of the normal or abnormal operation of the set of switches of matrix structure.

    摘要翻译： 输入线（I0〜I7）通过输入数据锁存器（1）连接到空间开关（2）。 空间开关（2）连接到通过串行/并行转换电路（3），公共缓冲存储器（4）连接到正常/测试转换开关（13）的正常/测试转换开关（12） 和并行到串行转换电路（5）。 空间开关（6）连接到正常/测试切换开关（13）。 输出线（O0至O7）通过输出数据锁存器（8）连接到空间开关6。 开关（2,6）中的连接状态在测试操作中通过转置连接发生电路（10）彼此置换，使得开关（2,6）通过开关彼此直接相连 （12,13）。 对输入线路应用的预定数据完全用作用于判断矩阵结构的开关组的正常或异常操作的预期值。

    Delay locked loop circuit
    10.
    发明授权
    Delay locked loop circuit 失效
    延时锁定回路电路

    公开(公告)号：US5994934A

    公开(公告)日：1999-11-30

    申请号：US111875

    申请日：1998-07-08

    申请人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe ,  Harufusa Kondoh ,  Hiromi Notani

    发明人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe ,  Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： G06F1/10 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/095 ,  H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/095

    摘要： Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.

    摘要翻译： 提供了可以在不增加延迟线的可变延迟时间范围的情况下执行精确的延迟同步操作的DLL电路。 DLL电路包括相位比较器（3），电荷泵（6），LPF（8）和延迟线（9），并且操作以匹配输入信号（CLKIN）和反馈信号（FBCLK）的相位， 。 相位比较器（3）总是输出在复位操作之后的初始操作时延迟线（9）的延迟时间增加的相位比较结果。 在执行复位时，LPF（8）输出指示由于延迟线（9）引起的延迟时间变为最小的延迟调整信号（S8）。