公开(公告)号：US20050133834A1

公开(公告)日：2005-06-23

申请号：US10948747

申请日：2004-09-24

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66636 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842

摘要： A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

摘要翻译： 本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于 通道层。

公开(公告)号：US20050040436A1

公开(公告)日：2005-02-24

申请号：US10866093

申请日：2004-06-14

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/8238 ,  H01L27/10

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US07564073B2

公开(公告)日：2009-07-21

申请号：US11294566

申请日：2005-12-06

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L27/04

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US07119417B2

公开(公告)日：2006-10-10

申请号：US10948747

申请日：2004-09-24

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L31/117

CPC分类号： H01L29/66636 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842

摘要： A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

摘要翻译： 本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于 通道层。

公开(公告)号：US07087473B2

公开(公告)日：2006-08-08

申请号：US10866093

申请日：2004-06-14

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L29/80

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US20060086988A1

公开(公告)日：2006-04-27

申请号：US11294566

申请日：2005-12-06

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US07554139B2

公开(公告)日：2009-06-30

申请号：US11568404

申请日：2005-04-11

申请人： Akira Inoue ,  Haruyuki Sorada ,  Yoshio Kawashima ,  Takeshi Takagi

发明人： Akira Inoue ,  Haruyuki Sorada ,  Yoshio Kawashima ,  Takeshi Takagi

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088

摘要： A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed. Step (A) includes step (a1) of forming, in the isolation region 70, a plurality of dummy regions 80 surrounded by the device isolation structure (STI), and step (B) includes step (b1) of growing a layer of the same material as that of the epitaxial layer on selected regions among the plurality of dummy regions 80.

摘要翻译： 根据本发明的半导体器件的制造方法包括：步骤（A），其提供包括具有主面的半导体层的衬底，所述衬底具有形成在隔离区域70中的器件隔离结构（STI），用于分割 主面进入多个设备有源区域50,60; 在半导体层的主面的多个器件有源区50,60中的选定器件有源区50上生长含有Si和Ge的外延层的工序（B） 以及在多个器件有源区域50,60之间形成晶体管的步骤（C），在其上形成有外延层的器件有源区域50中的每一个，外延层上的每个器件有源区域A2 没有形成。 步骤（A）包括在隔离区域70中形成被器件隔离结构（STI）包围的多个虚拟区域80的步骤（a1），步骤（B）包括步骤（b1） 与多个虚拟区域80中的选定区域上的外延层相同的材料。

公开(公告)号：US20080135877A1

公开(公告)日：2008-06-12

申请号：US11568404

申请日：2005-04-11

申请人： Akira Inoue ,  Haruyuki Sorada ,  Yoshio Kawashima ,  Takeshi Takagi

发明人： Akira Inoue ,  Haruyuki Sorada ,  Yoshio Kawashima ,  Takeshi Takagi

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088

摘要： A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed. Step (A) includes step (a1) of forming, in the isolation region 70, a plurality of dummy regions 80 surrounded by the device isolation structure (STI), and step (B) includes step (b1) of growing a layer of the same material as that of the epitaxial layer on selected regions among the plurality of dummy regions 80.

摘要翻译： 根据本发明的半导体器件的制造方法包括：步骤（A），其提供包括具有主面的半导体层的衬底，所述衬底具有形成在隔离区域70中的器件隔离结构（STI），用于分割 主面进入多个设备有源区域50,60; 在半导体层的主面的多个器件有源区50,60中的选定器件有源区50上生长含有Si和Ge的外延层的工序（B） 以及在多个器件有源区域50,60中形成晶体管的步骤（C），在其上形成有外延层的器件有源区域50中的每个器件有源区域A 2上，其上的外延层 没有形成。 步骤（A）包括在隔离区域70中形成被器件隔离结构（STI）包围的多个虚拟区域80的步骤（a1），步骤（B）包括步骤（b1） 与多个虚拟区域80中的选定区域上的外延层相同的材料。

公开(公告)号：US08013711B2

公开(公告)日：2011-09-06

申请号：US12280013

申请日：2007-02-27

申请人： Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

发明人： Zhiqiang Wei ,  Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima

IPC分类号： H01C7/10

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1683 ,  Y10T29/49099

摘要： A method for manufacturing a variable resistance element includes the steps of: depositing a variable resistance material (106) in a contact hole (105), which is formed on an interlayer insulating layer (104) on a substrate and has a lower electrode (103) at a bottom portion thereof, such that an upper surface of the variable resistance material (106) in the contact hole (105) is located lower than an upper surface of the interlayer insulating layer (104); depositing an upper electrode material on the deposited variable resistance material (106) such that an upper surface of the upper electrode material in the contact hole (105) is located higher than the upper surface of the interlayer insulating layer (104); and element-isolating by a CMP the variable resistance element including the variable resistance material (106) and the upper electrode material.

摘要翻译： 一种制造可变电阻元件的方法包括以下步骤：将可变电阻材料（106）沉积在形成在衬底上的层间绝缘层（104）上的接触孔（105）中，并具有下电极（103） ），使得所述接触孔（105）中的所述可变电阻材料（106）的上表面位于所述层间绝缘层（104）的上表面以下。 在所述沉积的可变电阻材料（106）上沉积上电极材料，使得所述接触孔（105）中的上电极材料的上表面位于比所述层间绝缘层（104）的上表面高; 以及通过CMP对包括可变电阻材料（106）和上电极材料的可变电阻元件进行元件隔离。

公开(公告)号：US07919774B2

公开(公告)日：2011-04-05

申请号：US12709148

申请日：2010-02-19

申请人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

发明人： Yoshio Kawashima ,  Takeshi Takagi ,  Takumi Mikawa ,  Zhiqiang Wei

IPC分类号： H01L29/68 ,  H01L21/34

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1658 ,  H01L45/1675

摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

摘要翻译： 设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。 金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及 具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。