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    Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder
    2.
    发明申请
    Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder 有权
    支持LDPC（低密度奇偶校验）解码器中的位节点和校验节点处理的公共电路

    公开(公告)号：US20050268206A1

    公开(公告)日：2005-12-01

    申请号：US11171568

    申请日：2005-06-30

    申请人： Hau Thien Tran ,  Kelly Cameron ,  Ba-Zhong Shen

    发明人： Hau Thien Tran ,  Kelly Cameron ,  Ba-Zhong Shen

    IPC分类号： G06K5/04 ,  G11B5/00 ,  G11B20/20 ,  H03M13/00 ,  H03M13/11 ,  H04L27/18 ,  H04L27/34

    CPC分类号： H04L27/34 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/658 ,  H04L27/18

    摘要： Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to perform updating of edge messages with respect to bit nodes as well as updating of edge messages with respect to check nodes in the context of decoding LDPC coded signals. In addition, several very efficient architectures are presented to performing check node processing that involves the updating of edge messages with respect to check nodes. One embodiment performs check node processing using min** (min-double-star) processing in conjunction with min**− (min-double-star-minus) processing. Another embodiment performs check node processing using min†† (min-double-dagger) processing in conjunction with min†− (min-dagger-minus) processing. In addition, a single FIFO may be implemented to service a number of macro blocks in a parallel decoding implementation.

    摘要翻译： 支持LDPC（低密度奇偶校验）解码器中的位节点和校验节点处理的公共电路。 提出了一种新颖的方法，其中解码器可以使用相同的电路来执行相对于位节点的边缘消息的更新，以及在解码LDPC编码信号的上下文中关于校验节点的边缘消息的更新。 此外，提出了几个非常有效的架构来执行涉及到关于校验节点的边缘消息的更新的校验节点处理。 一个实施例使用min **（min-double-star）处理结合min ** - （min-double-star-minus）处理来执行校验节点处理。 另一个实施例使用min††（最小双匕首）处理结合最小† - （最小匕首 - 减号）处理来执行校验节点处理。 此外，可以实现单个FIFO以在并行解码实现中服务多个宏块。

    Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes
    3.
    发明申请
    Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes 审中-公开
    消息传递存储器和桶形移位器布置在支持多个LDPC码的LDPC（低密度奇偶校验）解码器中

    公开(公告)号：US20060085720A1

    公开(公告)日：2006-04-20

    申请号：US11171569

    申请日：2005-06-30

    申请人： Hau Thien Tran ,  Kelly Cameron ,  Ba-Zhong Shen

    发明人： Hau Thien Tran ,  Kelly Cameron ,  Ba-Zhong Shen

    IPC分类号： H03M13/00

    CPC分类号： H03M13/658 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1137 ,  H03M13/1165

    摘要： Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes. A novel approach is presented by which a barrel shifter may be implemented in conjunction with a single message passing memory within an LDPC decoder. This arrangement also allows for a single bit/check processor to be employed that is operable to perform updating of edge messages with respect to check nodes as well as updating of edge messages with respect to bit nodes. There are a variety of embodiments by which the barrel shifter and the message passing memory may be implemented. By using this approach, a common architecture and design may operate to decode various types of LDPC coded signals including those whose code rate and/or modulation (including constellation shape and mapping) may vary as frequently as on a frame by frame basis or even on a block by block basis.

    摘要翻译： 消息传递存储器和桶形移位器布置在支持多个LDPC码的LDPC（低密度奇偶校验）解码器中。 提出了一种新颖的方法，通过该方法可以结合在LDPC解码器内传递存储器的单个消息来实现桶形移位器。 这种布置还允许采用单个位/检查处理器，该处理器可操作以相对于检查节点执行边缘消息的更新，以及相对于比特节点更新边缘消息。 可以实现桶形移位器和消息传递存储器的各种实施例。 通过使用这种方法，通常的架构和设计可以操作来解码各种类型的LDPC编码信号，包括其码率和/或调制（包括星座形状和映射）可能随着逐帧的变化而变化，或者甚至在 逐块的基础。

    Rate control adaptable communications
    4.
    发明授权
    Rate control adaptable communications 有权
    速率控制适应通信

    公开(公告)号：US08898547B2

    公开(公告)日：2014-11-25

    申请号：US12463386

    申请日：2009-05-09

    申请人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

    发明人： Kelly Brian Cameron ,  Ba-Zhong Shen ,  Hau Thien Tran

    IPC分类号： H03M13/00 ,  H03M13/39 ,  H03M13/29 ,  H03M13/25

    CPC分类号： H03M13/3905 ,  H03M13/256 ,  H03M13/258 ,  H03M13/2957 ,  H03M13/3988 ,  H03M13/6362 ,  H03M13/6516

    摘要： Rate control adaptable communications. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single decoder is operable to decode each of the various rates at which the data is encoded by the encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on a variety of operational parameters including operating conditions of the communication system, a change in signal to noise ratio (SNR), etc.

    摘要翻译： 速率控制适应通信。 在通信系统（编码器和解码器）的两端采用通用网格，以不同速率对数据进行编码和解码。 编码采用单个编码器，其输出位可以被选择性地打孔以支持根据速率控制序列的多个调制（星座和映射）。 单个解码器可操作以解码编码器对数据进行编码的各种速率中的每一个。 速率控制序列可以包括在编码和解码期间重复的周期中布置的速率控制的数量。 编码器和解码器中的一个或两者可以基于包括通信系统的操作条件，信噪比（SNR）等的变化的各种操作参数自适应地选择新的速率控制序列。

    LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices
    5.
    发明授权
    LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices 有权
    具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码

    公开(公告)号：US08370731B2

    公开(公告)日：2013-02-05

    申请号：US13423381

    申请日：2012-03-19

    申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

    发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

    IPC分类号： G06F11/10

    CPC分类号： H03M13/1174 ,  H03M13/1151 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1515 ,  H04L1/0068

    摘要： LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译： 具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成，并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI（循环移位身份）子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上，另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵（即，其中的所有元素是0的值）。

    Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder
    8.
    发明申请
    Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder 有权
    重叠的基于子矩阵的LDPC（低密度奇偶校验）解码器

    公开(公告)号：US20100138721A1

    公开(公告)日：2010-06-03

    申请号：US12651453

    申请日：2010-01-01

    申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

    发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

    IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/05

    CPC分类号： H03M13/1162 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/1185 ,  H03M13/616 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583

    摘要： Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

    摘要翻译： 重叠的基于子矩阵的LDPC（低密度奇偶校验）解码器。 提出了新的解码方法，通过该方法，立即采用对应于LDPC矩阵的子矩阵的更新的位边消息来更新与该子矩阵相对应的校验边消息，而不需要存储位边消息; 立即采用对应于LDPC矩阵的子矩阵的更新的校验边消息来更新与该子矩阵相对应的位边消息，而不需要存储校验边消息。 与执行整个LDPC矩阵的所有校验边消息的更新的系统相比，使用这种方法，在给定时间段内可以执行两倍的解码迭代，然后更新整个LDPC矩阵的所有位边消息，以及 所以。 当结合最小和处理执行这种重叠方法时，也可以节省大量的内存。

    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices
    9.
    发明申请
    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices 失效
    具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码

    公开(公告)号：US20090327847A1

    公开(公告)日：2009-12-31

    申请号：US12533306

    申请日：2009-07-31

    申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

    发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

    IPC分类号： G06F11/10

    CPC分类号： H03M13/1174 ,  H03M13/1151 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1515 ,  H04L1/0068

    摘要： LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译： 具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成，并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI（循环移位身份）子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上，另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵（即，其中的所有元素为零“0”）。

    FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS
    10.
    发明申请
    FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS 有权
    用于FEC（前向纠错）编码的固定间隔奇偶校验插入

    公开(公告)号：US20090193312A1

    公开(公告)日：2009-07-30

    申请号：US12021911

    申请日：2008-01-29

    申请人： Tak K. Lee ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

    发明人： Tak K. Lee ,  Ba-Zhong Shen ,  Hau Thien Tran ,  Kelly Brian Cameron

    IPC分类号： H04L1/18

    CPC分类号： H04L1/0043 ,  H04L1/0057 ,  H04L1/009

    摘要： Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities.

    摘要翻译： 用于FEC（前向纠错）码字的固定间隔奇偶校验插入。 当产生码字时，使用固定间隔来分散信息比特之间的奇偶比特。 根据该固定间隔，在码字中的每个奇偶校验位之间放置相同数量的信息比特。 如果需要，奇偶校验位的顺序可以在它们被置入码字之前改变。 此外，信息比特的顺序也可以在它们被置入码字之前被修改。 用于从信息比特生成奇偶校验位的FEC编码可以是各种代码中的任何一种，包括里德 - 所罗门（RS）码，LDPC（低密度奇偶校验）码，turbo码，turbo格状编码调制（TTCM） 或提供FEC能力的一些其他代码。