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    DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORY
    1.
    发明申请
    DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORY 有权
    检测电子存储器中的随机电视噪声诱发故障

    公开(公告)号：US20130019132A1

    公开(公告)日：2013-01-17

    申请号：US13183471

    申请日：2011-07-15

    申请人： Karen AMIRKHANYAN ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

    发明人： Karen AMIRKHANYAN ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

    IPC分类号： G11C29/10 ,  G06F11/263

    CPC分类号： G11C29/08 ,  G11C11/41 ,  G11C29/10

    摘要： A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

    摘要翻译： 一种用于测试电子存储器的方法和系统。 该方法包括使电子存储器经受预定的一组测试条件的第一测试条件。 该方法还包括使用预定的测试算法对于第一测试条件首次多次测试电子存储器的功能。 该方法还包括如果电子存储器的功能是令人满意的，则从预定的测试条件组检查第二测试条件的可用性。 此外，该方法包括如果第二测试条件可用，则使用预定测试算法来测试第二测试条件的电子存储器的功能，第二多次。 此外，如果电子存储器的功能令人满意，则该方法包括接受用于产品的电子存储器。

    Determining a desirable number of segments for a multi-segment single error correcting coding scheme
    2.
    发明授权
    Determining a desirable number of segments for a multi-segment single error correcting coding scheme 有权
    确定多段单纠错编码方案的期望数目的段

    公开(公告)号：US09053050B2

    公开(公告)日：2015-06-09

    申请号：US13310479

    申请日：2011-12-02

    申请人： Hayk Grigoryan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    发明人： Hayk Grigoryan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    IPC分类号： G06F12/10 ,  G06F11/10

    CPC分类号： G06F11/1048

    摘要： A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.

    摘要翻译： 基于用于存储器的加扰信息来确定用于多段单纠错（SEC）编码方案的段的期望数量。 期望数量的段可以是满足掩蔽的写分割要求和多位不匹配大小要求所需的最小段数。 在一个方面，存储器加扰信息可以指定存储器采用的不同的加扰技术（例如，输入 - 输出（IO）信元加扰，列加扰，列扭转，带分配等）。 基于加扰信息，可以导出存储器的逻辑结构和物理布局之间的映射。 该映射可用于确定满足掩蔽写入要求和多位不匹配大小要求所需的最少段数。

    Detecting random telegraph noise induced failures in an electronic memory
    3.
    发明授权
    Detecting random telegraph noise induced failures in an electronic memory 有权
    检测电子存储器中的随机电报噪声引起的故障

    公开(公告)号：US08850277B2

    公开(公告)日：2014-09-30

    申请号：US13183471

    申请日：2011-07-15

    申请人： Karen Amirkhanyan ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

    发明人： Karen Amirkhanyan ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

    IPC分类号： G11C29/00 ,  G11C29/08 ,  G11C29/10 ,  G11C11/41

    CPC分类号： G11C29/08 ,  G11C11/41 ,  G11C29/10

    摘要： A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

    摘要翻译： 一种用于测试电子存储器的方法和系统。 该方法包括使电子存储器经受预定的一组测试条件的第一测试条件。 该方法还包括使用预定的测试算法对于第一测试条件首次多次测试电子存储器的功能。 该方法还包括如果电子存储器的功能是令人满意的，则从预定的测试条件组检查第二测试条件的可用性。 此外，该方法包括如果第二测试条件可用，则使用预定测试算法来测试第二测试条件的电子存储器的功能，第二多次。 此外，如果电子存储器的功能令人满意，则该方法包括接受用于产品的电子存储器。

    Determining A Desirable Number Of Segments For A Multi-Segment Single Error Correcting Coding Scheme
    4.
    发明申请
    Determining A Desirable Number Of Segments For A Multi-Segment Single Error Correcting Coding Scheme 有权
    确定多段单纠错编码方案的期望数目

    公开(公告)号：US20130145119A1

    公开(公告)日：2013-06-06

    申请号：US13310479

    申请日：2011-12-02

    申请人： Hayk Grigoryan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    发明人： Hayk Grigoryan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    IPC分类号： G06F12/10

    CPC分类号： G06F11/1048

    摘要： A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.

    摘要翻译： 基于用于存储器的加扰信息确定用于多段单纠错（SEC）编码方案的段的期望数量。 期望数量的段可以是满足掩蔽的写分割要求和多位不匹配大小要求所需的最小段数。 在一个方面，存储器加扰信息可以指定存储器采用的不同的加扰技术（例如，输入 - 输出（IO）信元加扰，列加扰，列扭转，带分配等）。 基于加扰信息，可以导出存储器的逻辑结构和物理布局之间的映射。 该映射可用于确定满足掩蔽写入要求和多位不匹配大小要求所需的最少段数。

    Generation of memory structural model based on memory layout
    5.
    发明授权
    Generation of memory structural model based on memory layout 有权
    基于内存布局生成内存结构模型

    公开(公告)号：US09514258B2

    公开(公告)日：2016-12-06

    申请号：US13531189

    申请日：2012-06-22

    申请人： Karen Amirkhanyan ,  Karen Darbinyan ,  Arman Davtyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    发明人： Karen Amirkhanyan ,  Karen Darbinyan ,  Arman Davtyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/14

    摘要： A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.

    摘要翻译： 存储器结构模型以有效的方式直接从存储器配置信息和存储器布局信息生成。 通过分析存储器的配置信息和相应的存储器布局来生成带分布的信息。 通过使用物理位模式对存储器布局进行编程，提取对应的逻辑位模式，然后分析物理位模式与逻辑位模式之间的差异来产生关于存储器布局中地址加扰的信息。 带分布信息和地址扰乱信息被组合到用于设计有效的测试和修复引擎的存储器结构模型中。

    Generation of Memory Structural Model Based on Memory Layout
    6.
    发明申请
    Generation of Memory Structural Model Based on Memory Layout 有权
    基于内存布局的内存结构模型生成

    公开(公告)号：US20130346056A1

    公开(公告)日：2013-12-26

    申请号：US13531189

    申请日：2012-06-22

    申请人： Karen Amirkhanyan ,  Karen Darbinyan ,  Arman Davtyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    发明人： Karen Amirkhanyan ,  Karen Darbinyan ,  Arman Davtyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/14

    摘要： A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.

    摘要翻译： 存储器结构模型以有效的方式直接从存储器配置信息和存储器布局信息生成。 通过分析存储器的配置信息和相应的存储器布局来生成带分布的信息。 通过使用物理位模式对存储器布局进行编程，提取对应的逻辑位模式，然后分析物理位模式与逻辑位模式之间的差异来产生关于存储器布局中地址加扰的信息。 带分布信息和地址扰乱信息被组合到用于设计有效的测试和修复引擎的存储器结构模型中。

    TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY
    7.
    发明申请
    TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY 审中-公开
    基于故障和测试算法周期测试电子记忆

    公开(公告)号：US20130019130A1

    公开(公告)日：2013-01-17

    申请号：US13183468

    申请日：2011-07-15

    申请人： Aram HAKHUMYAN ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    发明人： Aram HAKHUMYAN ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

    IPC分类号： G11C29/12 ,  G06F11/263 ,  G06F11/27

    CPC分类号： G11C29/18 ,  G06F11/27 ,  G11C29/10 ,  G11C29/16 ,  G11C29/36 ,  G11C2029/0405

    摘要： Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.

    摘要翻译： 基于故障和测试算法周期测试电子存储器。 用于测试电子存储器的处理器单元包括内置的自检（BIST）有限状态机，地址发生器，数据发生器，测试算法生成单元，可编程测试算法寄存器和测试算法寄存器控制单元 。 用于测试电子存储器的存储器包装单元包括操作解码器，数据比较器和正在测试的电子存储器。 该方法包括构建具有与测试机制相对应的列的故障周期表，以及与故障族对应的行。 根据相应的故障族和测试机制选择第一个三月测试序列和第三个三月测试序列，并应用于电子存储器。 根据第一个三月份测试序列和三月份测试序列的结果，测试中的电子存储器被确定为可接受的和不可接受的。

    CONNECTOR WITH ENCLOSURE FOR ELECTRICAL CONTACTING MEANS OF THE CONNECTOR
    8.
    发明申请
    CONNECTOR WITH ENCLOSURE FOR ELECTRICAL CONTACTING MEANS OF THE CONNECTOR 审中-公开
    连接器的连接器，用于连接器的电气接触装置

    公开(公告)号：US20130322827A1

    公开(公告)日：2013-12-05

    申请号：US13880667

    申请日：2011-10-20

    申请人： Karl-Heinz Reimann ,  Gurgen Harutyunyan ,  Ekkehard Schomburg ,  Dietmar Brunsch

    发明人： Karl-Heinz Reimann ,  Gurgen Harutyunyan ,  Ekkehard Schomburg ,  Dietmar Brunsch

    IPC分类号： G02B6/44

    CPC分类号： G02B6/4401 ,  H01R13/5202 ,  H01R13/5205 ,  H01R13/6666

    摘要： The invention relates to a connector (CON1, CON2) comprising a first enclosure (ENCL1_CON2P—1, ENCL1_CON1_P2) and at least one electrical contacting means (CE1_ou1, CE1_out—2, CP_out—1, CE1_in—1, CE1_in—2), the first enclosure (ENCL1_CON1_P1, ENCL1_CON1_P2) comprises an inlet (INL) for a first cable (CABLE1) and an outlet (OUTL) for the first cable (CABLE1), the first enclosure (ENCL1_CON1_P1, ENCL1_CON1_P2), the inlet (INL) and the outlet (OUTL) are adapted to completely enclose a first electrical connection between the at least one electrical contacting means (CE1_out—1, CE1_out—2, CP_out—1, CE1_in—1, CE1_in—2) of the connector (CON1, CON2) and at least one conductor (COND_in, COND_out) of the first cable (CABLE1). The invention further relates to an assembly (ASBY1) comprising the connector (CON1, CON2) and the first cable (CABLE1) connected to the connector (CON1, CON2).

    摘要翻译： 本发明涉及包括第一外壳（ENCL1_CON2P-1，ENCL1_CON1_P2）和至少一个电接触装置（CE1_ou1，CE1_out-2，CP_out-1，CE1_in-1，CE1_in-2）的连接器（CON1，CON2） 第一外壳（ENCL1_CON1_P1，ENCL1_CON1_P2）包括用于第一电缆（CABLE1）的入口（INL）和用于第一电缆（CABLE1）的出口（OUTL），第一外壳（ENCL1_CON1_P1，ENCL1_CON1_P2），入口（INL） 插座（OUTL）适于完全包围连接器（CON1，CON2）的至少一个电接触装置（CE1_out-1，CE1_out-2，CP_out-1，CE1_in-1，CE1_in-2）之间的第一电连接， 以及第一电缆（CABLE1）的至少一个导体（COND_in，COND_out）。 本发明还涉及包括连接器（CON1，CON2）和连接到连接器（CON1，CON2）的第一电缆（CABLE1）的组件（ASBY1）。