公开(公告)号：US6031886A

公开(公告)日：2000-02-29

申请号：US137747

申请日：1998-08-21

申请人： Ji Ha Nah ,  Hee Young Jung ,  Bhum Cheol Lee ,  Kwon Chul Park

发明人： Ji Ha Nah ,  Hee Young Jung ,  Bhum Cheol Lee ,  Kwon Chul Park

IPC分类号： H03L7/00 ,  H04L7/033 ,  H03D3/24

CPC分类号： H04L7/0338

摘要： The present invention provides a digital phase alignment which to select the clock whose the transition is occured in the close vicinity of a center of the input data unit interval, the rising transition or falling transition of data are detected, as a result, to generate the synthetic clock retiming data upon detecting the transition of data having a random bit column, the retiming clock is reached in the center of eye pattern of data, compared with a single directional transition is detected.

摘要翻译： 本发明提供一种数字相位对准，其选择在输入数据单位间隔的中心附近发生转变的时钟，检测数据的上升转变或下降转换，结果产生 在检测到具有随机位列的数据的转变时的合成时钟重新定时数据，与检测到单个方向转换相比，在眼图数据的中心达到重新定时时钟。

公开(公告)号：US5703882A

公开(公告)日：1997-12-30

申请号：US571077

申请日：1995-12-12

申请人： Hee Young Jung ,  Bhum Cheol Lee ,  Kwon Chul Park

发明人： Hee Young Jung ,  Bhum Cheol Lee ,  Kwon Chul Park

IPC分类号： G06F11/00 ,  G06F11/10 ,  H03M13/00 ,  H04L1/00 ,  H04L7/04 ,  H04L7/08 ,  H04L12/70 ,  H04L25/03 ,  H04Q11/04

CPC分类号： H04L1/0061 ,  G06F11/10 ,  H04L1/0041 ,  H04L25/03866 ,  H04L7/048 ,  H04Q11/0478 ,  H04L2012/5673

摘要： A modified cyclic line coding apparatus for error detection and frame recovery which generates a n-bit modified cyclic cord-word by use of k redundancy bits and partially scrambles the cyclic redundancy check bits using periodic scramble bits. The apparatus includes a transmitter including a modified cyclic redundancy generator unit for generating redundancy bits, a variable period sampled scrambler unit for partially scrambling the redundancy bits, a timing control unit for generating a timing signal, and a multiplexer unit for multiplexing input cell data in accordance with the timing signal. The apparatus also includes a receiver including a modified cyclic redundancy checker unit for outputting a block synchronization signal and sample bits when a block synchronization is detected, while outputting a synchronization error signal when no block synchronization is detected, a variable period sampled descrambler unit for generating descramble bits in accordance with the sample bits, a timing recovering unit for generating a timing signal, and a demultiplexer unit for demultiplexing the cell data in accordance with the timing signal. The apparatus can use various cell sizes, can stably receive the user information of cell data and can achieve an easy bit timing detection.

摘要翻译： 一种用于错误检测和帧恢复的修改的循环线编码装置，其通过使用k个冗余比特生成n位修改的循环线字，并且使用周期性扰频比特部分地对循环冗余校验位进行加扰。 该装置包括：发射机，包括用于产生冗余比特的修改的循环冗余发生器单元，用于对冗余比特进行部分加扰的可变周期采样扰频单元，用于产生定时信号的定时控制单元，以及用于复用输入单元数据的多路复用器单元 根据定时信号。 该装置还包括一个接收机，包括一个修改的循环冗余校验器单元，用于当检测到块同步时输出块同步信号和采样位，同时在没有检测到块同步时输出同步误差信号;可变周期采样解扰器单元，用于产生 根据采样位的解扰位，用于产生定时信号的定时恢复单元和用于根据定时信号对单元数据解复用的解复用器单元。 该装置可以使用各种小区大小，可以稳定地接收小区数据的用户信息，并且可以实现容易的比特定时检测。

公开(公告)号：US5675293A

公开(公告)日：1997-10-07

申请号：US582882

申请日：1996-01-04

申请人： Bhum Cheol Lee ,  Jae Young Kim ,  Eun Chang Choi ,  Kwon Chul Park

发明人： Bhum Cheol Lee ,  Jae Young Kim ,  Eun Chang Choi ,  Kwon Chul Park

IPC分类号： H03K3/35 ,  H03K3/03 ,  H03B5/02

CPC分类号： H03K3/0315 ,  Y10S331/03

摘要： A voltage controlled ring oscillator having a reduced voltage controlled oscillator (VCO) gain by controlling only the fall time of the period of the VCO using integrated circuits and logic circuits. The VCO includes a mixer/inverter circuit, a logic circuit, a delay/inverter circuit, a first delay circuit, a second delay circuit, and a third delay circuit. The VCO gain is reduced by controlling only one pulse width of the logic level High and one pulse width of the logic level Low of the oscillating period. Furthermore, the VCO can be logically controlled by using a simple logic circuit as a component of the VCO.

摘要翻译： 通过仅使用集成电路和逻辑电路仅控制VCO的周期的下降时间，具有降压控制振荡器（VCO）增益的压控环形振荡器。 VCO包括混频器/反相器电路，逻辑电路，延迟/反相器电路，第一延迟电路，第二延迟电路和第三延迟电路。 通过仅控制逻辑电平高的一个脉冲宽度和振荡周期的逻辑电平低的一个脉冲宽度来减小VCO增益。 此外，可以通过使用简单的逻辑电路作为VCO的组件来逻辑地控制VCO。

公开(公告)号：US06366223B1

公开(公告)日：2002-04-02

申请号：US09350097

申请日：1999-07-09

申请人： Bhum Cheol Lee ,  Bong Soo Kim ,  Hee Bum Jung ,  Kwon Chul Park ,  Seok Youl Kang

发明人： Bhum Cheol Lee ,  Bong Soo Kim ,  Hee Bum Jung ,  Kwon Chul Park ,  Seok Youl Kang

IPC分类号： H03M700

CPC分类号： H03M5/04

摘要： A nibble inversion and block inversion code coding and decoding method and a coding and decoding apparatus for the same. The apparatus includes a disparity calculator for receiving a pre-code in which a nibble-inverted indication (NII) bit is added at the position next to the LSB of a source data of a n-bit (n represents an odd number higher than 3), computing a disparity Dpc value of the pre-code, computing a disparity value Dni of the odd bit nibble-inverted pre-code, decoding a code type in accordance with the value of the register and the value of the running digital sum RDS which represent the disparity code and outputting a control signal for manipulating the bits of the pre-code; a RDS calculator for outputting a RDS value which is obtained by accumulatively summing the disparity of the calculated code word by the unit of blocks for selecting a code word or a complement code word when the computed disparity Dpc is not 0; and a bit manipulator for selecting a nibble-inverted and block-inverted (NIBI) code type in accordance with a control signal from the disparity calculator, manipulating a bit of the inputted pre-code and generating a code word or a complement code word, for thereby providing a transition and a DC spectrum component of 0, using a 1-bit redundancy bit when a predetermined n-bit (n represents odd number) is coded, providing multiple frame patterns, and fully providing an in-band and out-band signal.

摘要翻译： 一种半字节反转和块反转码编码和解码方法及其编码和解码装置。 该装置包括：视差计算器，用于接收在n比特的源数据的LSB旁边的位置附加了半字节反转指示（NII）比特的预编码（n表示高于3的奇数） ），计算预编码的视差Dpc值，计算奇数比特半字节反相前置码的视差值Dni，根据寄存器的值解码码类型和运行数字和RDS的值 其代表差异码并输出用于操纵前置码的位的控制信号; RDS计算器，用于输出当所计算的视差Dpc不为0时通过用于选择代码字或补码的单元的单元累积求和所计算的代码字的视差获得的RDS值; 以及用于根据来自视差计算器的控制信号选择半字节反转和块反转（NIBI）码类型的位操纵器，操纵输入的预编码的位并产生码字或补码字， 从而提供转换和DC频谱分量为0，当预定的n位（n表示奇数）被编码时，使用1位冗余位，提供多个帧模式，并且完全提供带内和外部 频带信号。

公开(公告)号：US6104326A

公开(公告)日：2000-08-15

申请号：US136734

申请日：1998-08-19

申请人： Bhum Cheol Lee ,  Eun Chang Choi ,  Kwon Chul Park

发明人： Bhum Cheol Lee ,  Eun Chang Choi ,  Kwon Chul Park

IPC分类号： H03L7/00 ,  H03B27/00 ,  H03M5/06

CPC分类号： H03L7/0805 ,  H03L7/0995 ,  H04L7/0276 ,  H04L7/033

摘要： An apparatus for recovering high speed NRZ (non-return to zero) data is disclosed. A phase-locked loop (PLL) frequency-divides the frequency which is outputted from a voltage-controlled ring oscillator, and therefore, the physical limit of the PLL is not affected. The voltage-controlled ring oscillators are installed separately from the PLL, and the voltage-controlled ring oscillators are synchronized with the PLL in the frequency only. Further, the oscillators are phase-locked to the incoming NRZ data, and two voltage-controlled ring oscillators are enabled/disabled by the binary values of the NRZ data. Therefore, a bit synchronization is realized, and thus, the voltage-controlled ring oscillators are directly controlled by the NRZ data. Consequently, the NRZ data can be recovered up to the frequency band at which the voltage-controlled ring oscillators and a D flip flop operate.

摘要翻译： 公开了一种用于恢复高速NRZ（不归零）数据的装置。 锁相环（PLL）频率分频从压控环形振荡器输出的频率，因此PLL的物理极限不受影响。 压控环形振荡器与PLL分开安装，压控环形振荡器仅与频率同步。 此外，振荡器被锁相到进入的NRZ数据，并且两个压控环形振荡器由NRZ数据的二进制值启用/禁用。 因此，实现位同步，因此，电压控制的环形振荡器由NRZ数据直接控制。 因此，NRZ数据可以恢复到压控环形振荡器和D触发器工作的频带。

公开(公告)号：US07313197B2

公开(公告)日：2007-12-25

申请号：US10855258

申请日：2004-05-26

申请人： Tae Sik Cheung ,  Jae Wook Lee ,  Woo Young Choi ,  Bhum Cheol Lee ,  Bong Tae Kim ,  Jong Hyun Lee

发明人： Tae Sik Cheung ,  Jae Wook Lee ,  Woo Young Choi ,  Bhum Cheol Lee ,  Bong Tae Kim ,  Jong Hyun Lee

IPC分类号： H04L25/49

CPC分类号： H04L25/03343

摘要： Provided are a data transceiver and method for performing equalization and pre-emphasis adaptive to the transmission characteristic of a transmitting part. The transceiver measures the signal attenuation characteristic of a transmission line of a receiving part using an input data signal input via the transmission line of the receiving part, decodes the distorted waveform of the input data signal, distorts the waveform of an output data signal beforehand using the measured signal attenuation characteristic of the transmission line of the receiving part, and transmits the output data signal via a transmission line of a transmitting part. Thus, when the output data signal is transmitted via the transmission line of the transmitting part, the waveform of the signal remains optimized.

摘要翻译： 提供了一种用于执行自适应发送部分的传输特性的均衡和预加重的数据收发器和方法。 收发器使用经由接收部分的传输线输入的输入数据信号来测量接收部分的传输线的信号衰减特性，解码输入数据信号的失真波形，预先使用输出数据信号的波形扭曲 接收部分的传输线的测量信号衰减特性，并通过发送部分的传输线发送输出数据信号。 因此，当经由发送部的传输线发送输出数据信号时，信号的波形保持最优化。

公开(公告)号：US20100086091A1

公开(公告)日：2010-04-08

申请号：US12575375

申请日：2009-10-07

申请人： Dae Geun Park ,  Jung Hee Lee ,  Seung Woo Lee ,  Bhum Cheol Lee

发明人： Dae Geun Park ,  Jung Hee Lee ,  Seung Woo Lee ,  Bhum Cheol Lee

IPC分类号： H04L7/00

CPC分类号： G04R20/18 ,  H04J3/0667 ,  H04L69/28

摘要： Provided is a method and apparatus for synchronizing a time of day (TOD) in a convergent network, wherein the TOD is received from a time server connected in the convergent network and is provided to a terminal connected in a wired or wireless network, specifically a terminal connected in a heterogeneous network, that requires TOD information. The apparatus includes a time server that provides standard TOD information, a gateway or a host personal computer (PC) that provides the standard TOD information of the time server to the terminal in a 3rd layer or lower instead of an upper layer of the open system interconnection (OSI) 7 layer model, and the terminal that adjusts a local clock according to the provided standard TOD information. According to the method and apparatus, the terminal not only maintains a very precise TOD by obtaining TOD information of the time server periodically or when required, but also obtains the TOD information without using application software for processing the TOD information. Accordingly, power consumption of the terminal is decreased.

摘要翻译： 提供了一种用于在收敛网络中同步时间（TOD）的方法和装置，其中，从连接在会聚网络中的时间服务器接收TOD并将其提供给连接在有线或无线网络中的终端，具体地， 终端连接在异构网络中，需要TOD信息。 该装置包括提供标准TOD信息的时间服务器，网关或主机个人计算机（PC），其提供时间服务器的标准TOD信息到第三层或更低层的终端，而不是开放系统的上层 互连（OSI）7层模型，以及根据提供的标准TOD信息调整本地时钟的终端。 根据该方法和装置，终端不仅通过周期性地或者需要时间地获取时间服务器的TOD信息，而且在不使用用于处理TOD信息的应用软件的情况下获取TOD信息，来维持非常精确的TOD。 因此，终端的功耗降低。

公开(公告)号：US06633568B1

公开(公告)日：2003-10-14

申请号：US09494729

申请日：2000-01-31

申请人： Man Soo Han ,  Jung Hee Lee ,  Gab Joong Jeong ,  Bhum Cheol Lee

发明人： Man Soo Han ,  Jung Hee Lee ,  Gab Joong Jeong ,  Bhum Cheol Lee

IPC分类号： H04L1254

CPC分类号： H04L49/153 ,  H04L12/5601 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/254 ,  H04L49/255 ,  H04L49/30 ,  H04L49/3081 ,  H04L2012/5679 ,  H04L2012/5683

摘要： A two-dimensional round-robin scheduling method with multiple selection is provided. The two-dimensional round-robin scheduling method in accordance with an embodiment of the present invention includes following steps. First step is for checking whether a request is received from the input buffer module and building mxm request matrix r(i,j), i,j=1, . . . , m. Second step is for setting mxm search pattern matrix, d(i,j), i,j=1, . . . , m. The search pattern matrix describes search sequence, S=1, . . . , m. Third step is for initializing elements of mxm allocation matrix a(i,j), i,j=1, . . . , m. The allocation matrix contains information whether transmission request is accepted and which switching plane the accepted request uses in transmission. Fourth step is for examining a request matrix in accordance with the search sequence S and finding r(i,j) that sent a request. Fifth step is for setting a(i,j) for all (i,j) pairs found in the fourth step so that elements of allocation matrix at ith row have different values in range from 1 to n and elements of allocation matrix at jth column have different values in range from 1 to n. Sixth step is for repeating the fourth step and the fifth step as the search sequence S is increased from 1 to m by 1.

摘要翻译： 提供了一种具有多重选择的二维轮询调度方法。 根据本发明的实施例的二维轮询调度方法包括以下步骤。 第一步是检查是否从输入缓冲区模块接收请求，并建立mxm请求矩阵r（i，j），i，j = 1， 。 。 ，m。 第二步是设置mxm搜索模式矩阵，d（i，j），i，j = 1，。 。 。 ，m。 搜索模式矩阵描述了搜索序列S = 1。 。 。 ，m。 第三步是初始化mxm分配矩阵a（i，j），i，j = 1，...的元素。 。 。 ，m。 分配矩阵包含传输请求是否被接受以及接受请求在传输中使用的切换平面的信息。 第四步是根据搜索序列S检查请求矩阵，并找到发送请求的r（i，j）。 第五步是为了在第四步中发现的所有（i，j）对设置一个（i，j），使得第i行的分配矩阵的元素在1到n的范围内具有不同的值，并且第j列的分配矩阵的元素 在1到n的范围内具有不同的值。 第六步是当搜索序列S从1增加到1时重复第四步和第五步骤。

公开(公告)号：US09025965B2

公开(公告)日：2015-05-05

申请号：US13335596

申请日：2011-12-22

申请人： Seung Woo Lee ,  Kwang Chun Choi ,  Woo Young Choi ,  Bhum Cheol Lee

发明人： Seung Woo Lee ,  Kwang Chun Choi ,  Woo Young Choi ,  Bhum Cheol Lee

IPC分类号： H04B10/00 ,  H03L1/00 ,  H03L7/093 ,  H03L7/099

CPC分类号： H03L1/00 ,  H03L7/093 ,  H03L7/0998 ,  H03L2207/06 ,  H03L2207/50

摘要： Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

摘要翻译： 公开了数字方案的锁相环（PLL）及其方法。 更具体地，公开了具有时间 - 数字转换器（TDC），数字环路滤波器（DLF）和数字控制振荡器（DCO）的数字锁相环，并且被设计为具有恒定的抖动特性 即使电路的工作状态根据工艺，电压，温度（PVT）变化而变化，也是其方法。

公开(公告)号：US20070053353A1

公开(公告)日：2007-03-08

申请号：US11321191

申请日：2005-12-29

申请人： Hyoung Il Lee ,  Dae Geun Park ,  Jeong Hee Lee ,  Bhum Cheol Lee

发明人： Hyoung Il Lee ,  Dae Geun Park ,  Jeong Hee Lee ,  Bhum Cheol Lee

IPC分类号： H04L12/56 ,  H04L12/66

CPC分类号： H04L12/4658 ,  H04L12/4654 ,  H04L45/302 ,  H04L45/502 ,  H04L47/10 ,  H04L47/2425 ,  H04L47/2441 ,  H04L47/31

摘要： A method of classifying packets by a subscriber and processing classified packet to provide fairness to subscribers is provided. In order to classify the packets by the subscriber, a subscriber identification tag is inserted into a predetermined portion of an Ethernet frame and the packets are classified using the subscriber identification tag. The classified packets are processed based on the classifying result. Accordingly, an intermediate node not directly connected to the subscriber can classify the packets by the subscriber even in an uncontrollably expanded subscriber network. Therefore, the subscriber network is simply and effectively managed while providing the fairness to the subscriber in processing packets and allocating bandwidth.

摘要翻译： 提供了一种由用户分类分组并处理分类分组以向用户提供公平性的方法。 为了对用户对分组进行分类，将用户识别标签插入到以太网帧的预定部分中，并且使用用户识别标签对分组进行分类。 根据分类结果处理分类数据包。 因此，即使在不受控制地扩展的用户网络中，直接连接到用户的中间节点也可以由用户对分组进行分类。 因此，用户网络简单有效地被管理，同时在处理分组和分配带宽时向用户提供公平性。