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    Non-volatile memory integrated circuit device and method of fabricating the same
    1.
    发明授权
    Non-volatile memory integrated circuit device and method of fabricating the same 失效
    非易失性存储器集成电路器件及其制造方法

    公开(公告)号：US07928492B2

    公开(公告)日：2011-04-19

    申请号：US11804329

    申请日：2007-05-17

    申请人： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

    发明人： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

    摘要翻译： 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，字和选择线，以及浮置结区域，位线接合区域和公共源极区域。 半导体衬底具有多个基本上矩形的场区域，并且每个大致矩形场区域的短边和长边分别平行于矩阵的行和列方向。 字线和选择线在半导体衬底上平行于行方向延伸，字线与沿行方向设置的多个基本上矩形的场区交叉，并且选择线部分地重叠大致矩形的场区域 矩阵，使得基本上场区域的长边的部分和基本上矩形的场区域的短边位于选择线下方。 在半导体衬底之间，在字线和选择线之间形成浮点结区，与浮置结区相对地形成位线结区域，并且与浮接区相对地形成公共源区。

    Non-volatile memory integrated circuit device and method of fabricating the same
    2.
    发明申请
    Non-volatile memory integrated circuit device and method of fabricating the same 失效
    非易失性存储器集成电路器件及其制造方法

    公开(公告)号：US20070267684A1

    公开(公告)日：2007-11-22

    申请号：US11804329

    申请日：2007-05-17

    申请人： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

    发明人： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

    摘要翻译： 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，字和选择线，以及浮置结区域，位线接合区域和公共源极区域。 半导体衬底具有多个基本上矩形的场区域，并且每个大致矩形场区域的短边和长边分别平行于矩阵的行和列方向。 字线和选择线在半导体衬底上平行于行方向延伸，字线与沿行方向设置的多个基本上矩形的场区交叉，并且选择线部分地重叠大致矩形的场区域 矩阵，使得基本上场区域的长边的部分和基本上矩形的场区域的短边位于选择线下方。 在半导体衬底之间，在字线和选择线之间形成浮点结区，与浮置结区相对地形成位线结区域，并且与浮接区相对地形成公共源极区。

    High voltage transistor and method of manufacturing the same
    6.
    发明申请
    High voltage transistor and method of manufacturing the same 失效
    高压晶体管及其制造方法

    公开(公告)号：US20050035404A1

    公开(公告)日：2005-02-17

    申请号：US10899371

    申请日：2004-07-26

    申请人： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L29/41 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L31/0328

    CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/7835

    摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.

    摘要翻译： 本发明涉及高压晶体管及其制造方法。 高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于 浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。

    Self aligned 1 bit local SONOS memory cell
    7.
    发明授权
    Self aligned 1 bit local SONOS memory cell 失效
    自对准1位本地SONOS存储单元

    公开(公告)号：US07768061B2

    公开(公告)日：2010-08-03

    申请号：US11600765

    申请日：2006-11-17

    申请人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

    摘要翻译： 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

    High voltage transistor and method of manufacturing the same
    8.
    发明授权
    High voltage transistor and method of manufacturing the same 失效
    高压晶体管及其制造方法

    公开(公告)号：US07221028B2

    公开(公告)日：2007-05-22

    申请号：US10899371

    申请日：2004-07-26

    申请人： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L29/72

    CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/7835

    摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.

    摘要翻译： 本发明涉及高压晶体管及其制造方法。 高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于 浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。

    Self-aligned 1 bit local SONOS memory cell and method of fabricating the same
    10.
    发明申请
    Self-aligned 1 bit local SONOS memory cell and method of fabricating the same 失效
    自对准1位本地SONOS存储单元及其制造方法

    公开(公告)号：US20050029574A1

    公开(公告)日：2005-02-10

    申请号：US10912046

    申请日：2004-08-06

    申请人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

    摘要翻译： 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。