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    High voltage transistor and method of manufacturing the same
    3.
    发明申请
    High voltage transistor and method of manufacturing the same 失效
    高压晶体管及其制造方法

    公开(公告)号：US20050035404A1

    公开(公告)日：2005-02-17

    申请号：US10899371

    申请日：2004-07-26

    申请人： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L29/41 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L31/0328

    CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/7835

    摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.

    摘要翻译： 本发明涉及高压晶体管及其制造方法。 高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于 浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。

    Method of manufacturing EEPROM cell
    4.
    发明授权
    Method of manufacturing EEPROM cell 失效
    制造EEPROM单元的方法

    公开(公告)号：US07238572B2

    公开(公告)日：2007-07-03

    申请号：US11096038

    申请日：2005-03-31

    申请人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825

    摘要： A method of manufacturing an EEPROM cell includes growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling oxide layer being disposed under the first conductive pattern; forming a gate oxide layer on sidewalls of the first conductive pattern and the substrate and forming a second conductive pattern on both sides of the first conductive pattern; forming a conductive layer for a floating gate by electrically connecting the first conductive pattern to the second conductive pattern; forming a coupling oxide layer on the conductive layer for the floating gate; forming a third conductive layer on the coupling oxide layer; and forming a select transistor and a control transistor by patterning the third conductive layer, the coupling oxide layer, and the conductive layer for the floating gate. The select transistor is spaced apart from the control transistor. The select transistor, which is formed on the tunneling oxide layer, includes a gate stack formed of a select gate, a first coupling oxide pattern, and a first floating gate, and the control transistor includes a gate stack formed of a control gate, a second coupling oxide pattern, and a second floating gate.

    摘要翻译： 制造EEPROM单元的方法包括在半导体衬底上生长第一氧化物层; 在所述第一氧化物层上形成第一导电层; 通过图案化所述第一导电层和所述第一氧化物层来形成第一导电图案和隧道氧化物层，所述隧穿氧化物层设置在所述第一导电图案下方; 在所述第一导电图案和所述基板的侧壁上形成栅氧化层，并在所述第一导电图案的两侧上形成第二导电图案; 通过将所述第一导电图案电连接到所述第二导电图案来形成用于浮置栅极的导电层; 在浮栅的导电层上形成耦合氧化物层; 在所述耦合氧化物层上形成第三导电层; 以及通过图案化第三导电层，耦合氧化物层和浮栅的导电层来形成选择晶体管和控制晶体管。 选择晶体管与控制晶体管间隔开。 形成在隧道氧化物层上的选择晶体管包括由选择栅极，第一耦合氧化物图案和第一浮置栅极形成的栅极堆叠，并且控制晶体管包括由控制栅极形成的栅极堆叠， 第二耦合氧化物图案和第二浮栅。

    Self aligned 1 bit local SONOS memory cell
    5.
    发明申请
    Self aligned 1 bit local SONOS memory cell 失效
    自对准1位本地SONOS存储单元

    公开(公告)号：US20070063267A1

    公开(公告)日：2007-03-22

    申请号：US11600765

    申请日：2006-11-17

    申请人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

    摘要翻译： 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

    Self-aligned 1 bit local SONOS memory cell and method of fabricating the same
    6.
    发明授权
    Self-aligned 1 bit local SONOS memory cell and method of fabricating the same 失效
    自对准1位本地SONOS存储单元及其制造方法

    公开(公告)号：US07141473B2

    公开(公告)日：2006-11-28

    申请号：US10912046

    申请日：2004-08-06

    申请人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

    摘要翻译： 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

    Self aligned 1 bit local SONOS memory cell
    8.
    发明授权
    Self aligned 1 bit local SONOS memory cell 失效
    自对准1位本地SONOS存储单元

    公开(公告)号：US07768061B2

    公开(公告)日：2010-08-03

    申请号：US11600765

    申请日：2006-11-17

    申请人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

    摘要翻译： 自对准1比特氧化硅氮氧化物硅（SONOS）单元及其制造方法在相邻SONOS单元之间具有高均匀性，因为当蚀刻1比特的字线时，氮化物层的长度不会由于未对准而变化 SONOS细胞。 在半导体衬底上形成形成字线侧壁的绝缘层图案，在其侧壁上形成用于栅极的字线。 使用自对准蚀刻间隔物蚀刻ONO层提供均匀的相邻SONOS电池。

    High voltage transistor and method of manufacturing the same
    9.
    发明授权
    High voltage transistor and method of manufacturing the same 失效
    高压晶体管及其制造方法

    公开(公告)号：US07221028B2

    公开(公告)日：2007-05-22

    申请号：US10899371

    申请日：2004-07-26

    申请人： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    发明人： Tae-kwang Yu ,  Hee-seog Jeon ,  Seung-beom Yoon ,  Yong-tae Kim

    IPC分类号： H01L29/72

    CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/7835

    摘要： The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.

    摘要翻译： 本发明涉及高压晶体管及其制造方法。 高压晶体管包括：形成在半导体衬底中的沟道区; 形成在半导体衬底的沟道区上的栅极绝缘膜; 低浓度源极区和低浓度漏极区，其间具有沟道区，并且各自形成在半导体衬底中; 高浓度源区，其形成为与沟道区隔开第一距离; 高浓度漏区，其形成为与沟道区隔开距离大于第一距离的第二距离; 栅极电极，其具有与沟道区域上的栅极绝缘膜接合的栅极底部，以及与栅极底部一体化并且从栅极底部的顶部突出预定长度的栅极顶部，以在低于 浓度排水区; 形成在高浓度源区上的第一金属硅化物层; 以及形成在高浓度漏极区上的第二金属硅化物层。