摘要:
The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.
摘要:
The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.
摘要:
A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.
摘要:
The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.
摘要:
A method of manufacturing an EEPROM cell includes growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling oxide layer being disposed under the first conductive pattern; forming a gate oxide layer on sidewalls of the first conductive pattern and the substrate and forming a second conductive pattern on both sides of the first conductive pattern; forming a conductive layer for a floating gate by electrically connecting the first conductive pattern to the second conductive pattern; forming a coupling oxide layer on the conductive layer for the floating gate; forming a third conductive layer on the coupling oxide layer; and forming a select transistor and a control transistor by patterning the third conductive layer, the coupling oxide layer, and the conductive layer for the floating gate. The select transistor is spaced apart from the control transistor. The select transistor, which is formed on the tunneling oxide layer, includes a gate stack formed of a select gate, a first coupling oxide pattern, and a first floating gate, and the control transistor includes a gate stack formed of a control gate, a second coupling oxide pattern, and a second floating gate.
摘要:
A semiconductor memory device having a self-aligned charge trapping layer and a method of manufacturing the same in which a consistent length of an ONO layer is ensured. Here, an insulating stacked structure is self-aligned to a bottom surface of conductive spacers.
摘要:
A method of manufacturing an EEPROM cell includes growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling oxide layer being disposed under the first conductive pattern; forming a gate oxide layer on sidewalls of the first conductive pattern and the substrate and forming a second conductive pattern on both sides of the first conductive pattern; forming a conductive layer for a floating gate by electrically connecting the first conductive pattern to the second conductive pattern; forming a coupling oxide layer on the conductive layer for the floating gate; forming a third conductive layer on the coupling oxide layer; and forming a select transistor and a control transistor by patterning the third conductive layer, the coupling oxide layer, and the conductive layer for the floating gate. The select transistor is spaced apart from the control transistor. The select transistor, which is formed on the tunneling oxide layer, includes a gate stack formed of a select gate, a first coupling oxide pattern, and a first floating gate, and the control transistor includes a gate stack formed of a control gate, a second coupling oxide pattern, and a second floating gate.
摘要:
A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.
摘要:
A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.
摘要:
A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.