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    Nonvolatile memory device and method of manufacturing the same
    2.
    发明申请
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20050162958A1

    公开(公告)日：2005-07-28

    申请号：US10975996

    申请日：2004-10-29

    申请人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

    发明人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

    IPC分类号： H01L21/8247 ,  G11C7/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

    CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

    摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

    摘要翻译： 提供一种非易失性存储器件及其制造方法。 该器件包括半导体衬底; 设置在所述半导体衬底中的源区和漏区以及置于所述源极和漏极区之间的沟道区; 设置在所述源极区附近的所述沟道区上的第一隧道氧化物层; 设置在漏区附近的沟道区上的第二隧道氧化层; 设置在第一隧道氧化物层上的第一电荷俘获层; 设置在所述第二隧道氧化物层上的第二电荷俘获层; 覆盖第一和第二电荷俘获层的阻挡氧化物层; 介于所述第一和第二电荷俘获层之间的电荷隔离层; 以及设置在阻挡氧化物层上的栅电极。

    Nonvolatile memory device and method of manufacturing the same
    3.
    发明申请
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20060273377A1

    公开(公告)日：2006-12-07

    申请号：US11504702

    申请日：2006-08-16

    申请人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

    发明人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

    IPC分类号： H01L29/788

    CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

    摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

    摘要翻译： 提供一种非易失性存储器件及其制造方法。 该器件包括半导体衬底; 设置在所述半导体衬底中的源区和漏区以及置于所述源极和漏极区之间的沟道区; 设置在所述源极区附近的所述沟道区上的第一隧道氧化物层; 设置在漏区附近的沟道区上的第二隧道氧化层; 设置在第一隧道氧化物层上的第一电荷俘获层; 设置在所述第二隧道氧化物层上的第二电荷俘获层; 覆盖第一和第二电荷俘获层的阻挡氧化物层; 介于所述第一和第二电荷俘获层之间的电荷隔离层; 以及设置在阻挡氧化物层上的栅电极。

    Nonvolatile memory device and method of manufacturing the same
    4.
    发明授权
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07208365B2

    公开(公告)日：2007-04-24

    申请号：US11504702

    申请日：2006-08-16

    申请人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

    发明人： Hee-soon Chae ,  Chung-woo Kim ,  Kwang-youl Seo ,  Tae-hyun Han ,  Byung-chul Kim ,  Joo-yeon Kim

    IPC分类号： H01L21/8238

    CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

    摘要： Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.

    摘要翻译： 提供一种非易失性存储器件及其制造方法。 该器件包括半导体衬底; 设置在所述半导体衬底中的源区和漏区以及置于所述源极和漏极区之间的沟道区; 设置在所述源极区附近的所述沟道区上的第一隧道氧化物层; 设置在漏区附近的沟道区上的第二隧道氧化层; 设置在第一隧道氧化物层上的第一电荷俘获层; 设置在所述第二隧道氧化物层上的第二电荷俘获层; 覆盖第一和第二电荷俘获层的阻挡氧化物层; 介于所述第一和第二电荷俘获层之间的电荷隔离层; 以及设置在阻挡氧化物层上的栅电极。

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110116334A1

    公开(公告)日：2011-05-19

    申请号：US12948302

    申请日：2010-11-17

    申请人： Je-min YU ,  Byung-chul Kim ,  Jun-hyung Kim ,  Sang-joon Hwang

    发明人： Je-min YU ,  Byung-chul Kim ,  Jun-hyung Kim ,  Sang-joon Hwang

    IPC分类号： G11C7/12 ,  G11C7/08

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

    摘要： A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

    摘要翻译： 半导体存储器件包括：位线检测放大器，用于检测和放大来自存储器单元的一对位线的数据;列选择单元，响应于列选择信号，将一对位线的数据传输到一对本地数据; 数据预充电单元响应于预充电信号将一对本地数据线预充电到预充电电压电平，以及数据感测放大器检测和放大传输到该对本地数据线的数据。 数据传感放大器包括电荷同步单元，响应于第一数据感测使能信号和一对本地数据的数据，以预充电电压电平放电该对本地数据线;以及数据感测单元，传输该对本地数据 响应于第二数据感测使能信号将数据传送到一对全局数据。

    Adaptive bandwidth phase locked loops with current boosting circuits
    6.
    发明授权
    Adaptive bandwidth phase locked loops with current boosting circuits 失效
    带电流升压电路的自适应带宽锁相环

    公开(公告)号：US07646226B2

    公开(公告)日：2010-01-12

    申请号：US11826901

    申请日：2007-07-19

    申请人： Byung-chul Kim

    发明人： Byung-chul Kim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0895

    摘要： An adaptive bandwidth phase locked loop (PLL) includes a phase frequency detector configured to generate a comparison pulse having a pulse-width and sign corresponding to a difference between a reference frequency and a first frequency. A pulse-voltage converter is configured to generate a control voltage corresponding to the comparison pulse. An oscillator is configured to generate the output frequency corresponding to the control voltage.

    摘要翻译： 自适应带宽锁相环（PLL）包括相位频率检测器，被配置为产生具有对应于参考频率和第一频率之间的差的脉冲宽度和符号的比较脉冲。 脉冲电压转换器被配置为产生对应于比较脉冲的控制电压。 振荡器被配置为产生对应于控制电压的输出频率。